Integrated cooling

One of the main efforts in the industry is to improve performance of cooling solutions while reducing their complexity and cost. This is particularly important for liquid cooling, which is composed of a solid liquid heat exchanger, pump, tubing, and liquid air heat exchanger.

We approach this topic by means of a cooler that integrates all components in the base of a finned air heat sink and can be produced by batch fabrication processes. This compact integrated hybrid cooler uses a novel flow scheme to spread heat with a much lower thermal resistance than coolers that use solid copper or vapor chambers. This novel cooler interfaces with the microprocessor chip and spreads heat over a large area, where it can be cooled using conventional fins and forced-air convection. The core exchange area directly in contact with the microprocessor chip consists of a highly optimized solid-to-liquid heat exchanger. Ongoing research is demonstrating the full potential of the novel concept in terms of cooling performance.

Reducing the dimensions of an integrated circuit on a chip also reduces the delay time of transistors but increases the delay time for electrical interconnects. The result is that, in future circuits, the delay time of global interconnects will limit the system performance. 3D integration of IC chips with interchip interconnects significantly reduces the global interconnect length and delay time and allows new IC architectures with highly parallel communication. for example from processor to cache or from CCD arrays to amplifiers. It also allows the combination of heterogeneous devices based on different technologies and having different functionality such as digital, analog and high-frequency circuits and logic, memory and IOs on different levels. This results in an increase in volumetric integration density, which also creates higher volumetric power densities.

A crucial task is to remove the dissipated power of each layer by a thin-film cooler. The cold plate design has to fulfill multiple constraints regarding

• heat and mass transfer to the electrical integrity of the signals traveling in the interchip interconnects,
• low mechanical coupling from level to level and
• compatibility with the IC fabrication processes and their packaging rules.

One of the most challenging constraints is the limited spacing between chips where the heat has to be removed. The goal is to design a low-pressure drop fluid path to minimize the pumping power while being able to remove high power densities.

1. T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann and H. Reichl, "Interlayer Cooling Potential in Vertically Integrated Packages," Microsystem Technol. 15(1) (2009) 57-74 (published online: August 21, 2008).
2. T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Reichl and H. Oppermann, "Hotspot Optimized Interlayer Cooling In Vertically Integrated Packages," in Proc. Materials Research Society (MRS) Fall Meeting 2008, Boston, MA, Vol. 112, E06-02.
3. T. Brunschwiler and B. Michel, "Thermal Management of Vertically Integrated Packages," in Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, edited by P. Garrou, C. Bower and P. Ramm (Wiley-VCH Verlag GmbH, Weinheim, 2008) Vol. 2, Part IV, pp. 635-649.
4. R. Wälchli, R. Linderman, T. Brunschwiler, U. Kloter, H. Rothuizen and B. Michel, "Radially Oscillating Flow Hybrid Cooling for Low Profile Electronics Applications," in Proc. 24th Annual IEEE Semionductor Thermal Measurement and Management Symp. 2008 "SEMI-THERM 2008," San Jose, CA, March 2008 (IEEE), pp. 142-148.
   
5. T. Brunschwiler, H. Rothuizen, U. Kloter, H. Reichl, B. Wunderle, H. Oppermann and B. Michel, "Forced Convective Interlayer Cooling Potential in Vertically Integrated Packages," in Proc. 11th Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems 2008 "ITHERM 2008," Orlando, FL, May 2008 (IEEE, 2008), pp. 1114-1125.

Nano-Tera CMOSAIC project

Figure 1. Hybrid cooler directly attached to processor chip with fluid layer (blue) integrated in base of heatsink.

Figure 2. Interlayer cooling of 3D-IC packages.