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One of the main efforts in the industry is to improve performance
of cooling solutions while reducing their complexity and cost. This
is particularly important for liquid cooling, which is composed
of a solid liquid heat exchanger, pump, tubing, and liquid air heat
exchanger.
Compact integrated hybrid coolers
We approach this topic by means of a cooler that integrates all
components in the base of a finned air heat sink and can be produced
by batch fabrication processes. This compact integrated hybrid cooler
uses a novel flow scheme to spread heat with a much lower thermal
resistance than coolers that use solid copper or vapor chambers.
This novel cooler interfaces with the microprocessor chip and spreads
heat over a large area, where it can be cooled using conventional
fins and forced-air convection. The core exchange area directly
in contact with the microprocessor chip consists of a highly optimized
solid-to-liquid heat exchanger. Ongoing research is demonstrating
the full potential of the novel concept in terms of cooling performance.
Cooling of stacked chips and packages
Reducing the dimensions of an integrated circuit on a chip also
reduces the delay time of transistors but increases the delay time
for electrical interconnects. The result is that, in future circuits,
the delay time of global interconnects will limit the system performance.
3D integration of IC chips with interchip interconnects significantly
reduces the global interconnect length and delay time and allows
new IC architectures with highly parallel communication. for example
from processor to cache or from CCD arrays to amplifiers. It also
allows the combination of heterogeneous devices based on different
technologies and having different functionality such as digital,
analog and high-frequency circuits and logic, memory and IOs on
different levels. This results in an increase in volumetric integration
density, which also creates higher volumetric power densities.
A crucial task is to remove the dissipated power of each layer
by a thin-film cooler. The cold plate design has to fulfill multiple
constraints regarding
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heat and mass transfer to the electrical integrity
of the signals traveling in the interchip interconnects, |
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low mechanical coupling from level to level and |
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compatibility with the IC fabrication processes
and their packaging rules. |
One of the most challenging constraints is the limited spacing
between chips where the heat has to be removed. The goal is to design
a low-pressure drop fluid path to minimize the pumping power while
being able to remove high power densities.
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