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Explosion of power density


Project overview

The continued growth and development of the semiconductor industry has relied primarily on the exponential increase in the density of solid-state integrated circuits. Decreasing the feature size of the unit transistor has allowed a dramatic improvement of the overall circuit performance and an equally significant reduction of cost per manufactured component. Moore's law has described this as an exponential growth with a doubling of transistor numbers every 18 months. Although such an exponential trend cannot continue indefinitely due to fundamental limits imposed by basic physics and technology, such barriers have to date been overcome by innovations. The dissipation of energy into heat has long been recognized as an issue that might limit information processing. Now, however, it seems this is the barrier that is the most difficult to break.

The graph shows how power density has been the decisive factor to end the development of bipolar transistors in favor of the CMOS technology, which resulted in devices with 3× lower peak performance but 15× lower power density. The red-green trend therefore remains hypothetical but highly desirable. Unfortunately there is no mature technology at this time that would allow a switch similar to the one developed fifteen years ago. For this reason, it seems only possible for innovations to limit the strong exponential growth of power density such that the power dissipations can be handled from innovations coming from thermal management research (red arrow).

The explosion of power density causes an increase in size of cooling equipment that is opposed to the general trend of shrinking sizes of electronic components. With improved cooling concepts we can break this trend and introduce coolers that are much smaller than those relying on conventional approaches.

» Back to High-performance thermal interfaces

Images, click to enlarge
    Evolution of power density as function of time for bipolar technology (blue) and CMOS technology (red) and for a hypothetical future technology (green).    
  Module heat flux  
    Size of heatsinks for different generations of processors increasing from 5×5×3 cm3 (left) to 20×20×20 cm3 (right).    
  Sizes of cooling units  

 

 References

[1] T. Brunschwiler, U. Kloter, H. Rothuizen, and B. Michel, "Hierarchically nested channels for fast squeezing interfaces with reduced thermal resistance," 21st IEEE SEMI-THERM Symposium, San Jose, CA (2000).
[2] T. Brunschwiler, U. Kloter, R. Linderman, H. Rothuizen, and B. Michel, "Hierarchically nested channels for fast squeezing interfaces with reduced thermal resistance," Trans. Comp. Packag. Technol., in press.
 
     
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