Overview
This part of the nanowire project at IBM Zurich focuses on the processing of semiconductor nanowires into functional devices, e.g. FETs. The main focus is directed toward vertical nanowire devices with surround gate geometry for optimum electrostatics [1]. Effort is being put into developing low-temperature gate dielectrics using ALD and CVD techniques for FEOL and BEOL Si technology compatibility, scaling of gate lengths and ohmic contact formation.
In addition, we are investigating lateral nanowire devices [2] with an emphasis on nanowire surface passivation and ohmic contact formation using, for example, implanted contacts.
The figure at right depicts schematically the lateral and vertical approach to nanowire devices.
References
[1] V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess, U. Gösele, Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor, Small 2(1) (January 2006) 85-88 (published online: 7 Nov 2005).
[2] O. Hayden, M. T. Björk, H. Schmid, H. Riel, U. Drechsler, S.F. Karg, E. Lörtscher, W. Riess, Fully-Depleted Nanowire Field Effect Transistor in Inversion Mode, Small 3, 230 (2007).
[3] M.T. Björk, O. Hayden, H. Schmid, H. Riel, W. Riess, Vertical Surround-Gated Silicon Nanowire Impact Ionization Field-Effect Transistors, Appl. Phys. Lett. 90, 142110 (2007).
