NEM switch technologies for low-power logic applications


Power consumption is a major bottleneck in state-of-the-art integrated microelectronic systems, with leakage power approaching dynamic power for deep-submicron technologies. Many solutions have been and are currently being explored to tackle this issue but, fundamentally, the energy efficiency of a CMOS FET is limited by its sub-threshold conduction characteristic. Nano electromechanical (NEM) switches have been proposed as a new switch technology to address this fundamental bottleneck. Intrinsically, such a technology could offer zero leakage, abrupt switching, and high ON-current at low operating voltage. Moreover, NEM switches have the potential to be more radiation-resistant and can withstand higher operating temperatures than CMOS. The design of NEM switches for logic applications needs to address many challenges, such as device size, operation voltage, operation speed, robustness, and contact resistance. Fundamentally, NEM switch energy efficiency is limited mainly by the adhesion of the electrical contact and the force required for breaking this adhesion [1]. Therefore, minimizing the contact size and the electrode-to-electrode interactions plays an important role in the minimum achievable power consumption of such devices.

We explore the design space to optimize silicon in-plane NEM switches for low-power applications and propose a curved cantilever design, see Figure 1, for electrostatically actuated switches [2]. Our design is compact and robust thanks to good control of the actuation gap in the closed position. The contact and actuation gap are not defined lithographically but rather through the thickness of the same sacrificial layer, enabling scalability to nanometer sizes. Tilting the actuation electrode with respect to the switch motion reduces the closing of the actuation gap (ON-capacitance) and the electric field from gate to cantilever in the closed position.

The work was partially supported by the European Union’s Seventh Framework Programme (FP7/2007-2011) under grant agreement No. 288670 named NEMIAC.


[1] E. Alon, et al. “Design, optimization, and scaling of mem relays for ultra-low-power digital logic,”  Electron Devices, IEEE Transactions on, 58(1):236–250, 2011.

[2] D. Grogg et al., “Curved cantilever design for a robust and scalable microelectromechanical switch,“ in Proc. 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, Waikoloa, Hawaii, 2012.