High-κ dielectrics

The gate stack used in current-generation, metal-oxide semiconductor field-effect transistors (MOSFET) consists of silicon, an insulating layer of silicon dioxide, and a metallic gate electrode made of polysilicon. The improvement of transistor performance during the past 40 years has been achieved mainly through geometrical scaling of this gate stack. This approach is running out of steam because the insulating silicon dioxide in current device generations has a thickness of only about five atomic layers. Owing to direct tunneling, the gate leakage current increases dramatically, thereby leading to a high current in the off-state of the transistors and significant heat dissipation. The operating frequency of the transistors can no longer be scaled according to Moore's law.

Future CMOS performance enhancements will result from materials innovation instead of pure scaling. New materials will be introduced in the gate stack: Layers with higher dielectric constant (so-called high-κ materials) will replace silicon dioxide as the gate dielectric. Amorphous HfO2-based films (κ~20) are candidates to be used first, and epitaxial materials with even higher dielectric constants could be used later. As a consequence of introducing high-κ dielectrics, the gate metal has to be changed from polysilicon to other metallic layers (TiN, TaN). Finally it will be necessary to replace silicon by a semiconducting material with higher carrier mobility such as Ge or III-V materials (GaAs, InAs).

One of our team activities is the investigation of new high-κ dielectric materials on silicon. We are working on amorphous (HfO2-based) and epitaxial materials like the perovskites SrTiO3, SrZrO3 and SrHfO3. For best device performances, the whole stack requires the right choice of materials, a precise control over the quality of the different layers and of their respective interfaces. Our choice of deposition technique is molecular beam epitaxy (MBE), which combines clean UHV conditions with a high versatility in growing new materials. We operate stand-alone, oxide-MBE systems and are currently building a complex 200-mm cluster MBE tool, which integrates growth chambers for GaAs, Si/Ge, and oxides in a UHV environment.

One of our challenges is to search for novel high-κ dielectric candidates with appropriate properties such as

and to fabricate long channel transistors with optimized properties, in particular high channel mobility at low equivalent oxide thicknesses (EOT).

The structural properties of the deposited layers are analyzed by reflection high energy electron diffraction (RHEED), X-ray diffractometry (XRD), ellipsometry, X-ray photoelectron spectroscopy (XPS), high-resolution transmission electron microscopy (HRTEM) and atomic force microscopy (AFM).

The electrical properties of our films (effective oxide thickness, leakage, carrier mobility) are derived from MOS capacitors and long-channel FETs, which we fabricate in-house, using our clean room facility. In particular current-voltage I-V and capacitance-voltage C-V measurements are performed using standard equipment. The trapped charges at the interface as well as in the bulk of the oxide are investigated by several techniques: among them the well-known peak conductance method on MOS structures and the pulse based charge pumping method on MOSFETs.

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