|
We have developed wafer-scale, 3D interconnect methods for the
batch fabrication of systems-on-chip (SoCs) especially suitable
for MEMS or VLSI-MEMS applications. This work is part of the development
of a highly parallel data-storage system based on a scanning-probe
array, and aims to interconnect the array cantilevers vertically
with their driving electronics fabricated on a separate CMOS electronic
circuit. A very high integration density has been achieved even
for wafer-scale joining (MEMS and CMOS wafers) thanks to the interlocking
nature of the interconnect structure developed, which provides easy
alignment with an accuracy of better than 2 µm. A typical
integration density achieved is 100 cantilevers/mm² and up
to 1000 electrical interconnects/mm².
In contrast to flip chip technology, this method preserves the
device orientation, which is crucial for MEMS applications, in which
the MEMS device should typically have access to its environment
(e.g. in this specific case, the cantilever tips are in contact
with the storage medium). Once the CMOS-MEMS joining has been performed,
the system is mechanically and electrically stable up to at least
400 °C, allowing post-joining wafer processing.
Figure 1 shows the microdevice transfer method with the example
of cantilevers. The goal is that the cantilever array is transferred
on a dedicated CMOS chip in order to have a very short path between
the cantilever and the driving/sensing integrated analog electronic.
The cantilever itself is fabricated in the silicon membrane of an
SOI wafer. The first step is the lamination of the wafer on a glass
wafer using a polymer-based adhesive technique. Next the silicon
wafer is removed, first by grinding and then, for the final tens
of micrometers, by plasma etching using the SOI buried oxide (BOX)
as etch stop. The BOX is subsequently wet-etched with BHF. Back-side
processing is performed to define a metal pad for the electrical
interconnection as well as a polyimide via. On the CMOS wafer side
a Cu/Sn stud is electroplated. The CMOS and the cantilevers wafer
are laminated together, using the stud/polyimide via as interlock
feature to provide the high alignment accuracy. Glass delamination
is done by a laser-ablation technique, using an excimer laser with
a wavelength at which the glass wafer, but not the polyimide, is
transparent. Hence while scanning the laser beam over the wafer
surface, a thin polyimide layer at the polyimide/Glass interface
is ablated, allowing the glass wafer, which can be reused after
cleaning, to be removed. Figure 2 shows a small section of the array
of cantilevers transferred (4096 cantilevers/array). They typically
are 70 µm long and 500 nm thick, have a tip with a sub-20-nm
radius, and the cantilever density is 100 per mm².
The robustness of the transfer technique developed for IBM Research's
probe-based storage project (see section B8.2.1) is a major step
towards highly integrated systems on chip (SOC), and opens up new
opportunities for MEMS and its integration with microelectronics.
It exhibits great potential for heterogeneous-device and 3D integration.
We believe that the unique advantage of transferring a sea of devices
rather than a chip with devices will result in new possibilities
to fabricate SOCs with greater functionalities by combining subsequent
device transfer with the integration of devices side by side and/or
vertically, and post-transfer processing (see Figure 3).
|
