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Following Moore's law, the shrinking of CMOS allows us to build
high-speed interconnect circuits at even higher data rates. We are
exploring new circuit architectures for transmitter and receiver
circuits together with next-generation CMOS technology. The goal
is to achieve the highest possible data rates at the lowest power
consumption on the smallest chip area.
Typical circuits include
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Transmitter/drivers circuits [4,6,7,11] with
integrated feed-forward equalization (FFE) |
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High-bandwidth input amplifiers/equalizer circuits
[1,2,6,7,9] |
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Receiver circuits with clock and data recovery
(CDR) capability [6,8,10,12] |
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Phase-locked loops (PLLs) for clock-generation
technology [3,5,8]. |
Selected publications
| [1] |
C. Kromer, G. Sialm, T. Morf, M. Schmatz, F.
Ellinger, D. Erni, H. Jäckel, "A low-power 20-GHz
52-dB transimpedance amplifier in 80-nm CMOS", IEEE Journal
of Solid-State Circuits, Volume 39, Issue 6, June 2004, pp.
885-894 |
| [2] |
T. Toifl, C. Menolfi, M. Kossel, T. Morf, M.
Schmatz, "A 23GHz differential amplifier with monolithically
integrated T-coils in 0.09µm CMOS technology", IEEE
Microwave Symposium Technical Digest, Philadelphia, June 2003 |
| [3] |
M. Kossel, T. Morf, W. Baumberger, A. Biber,
C. Menolfi, T. Toifl, M. Schmatz, "A multiphase PLL for
10 Gb/s links in SOI CMOS technology", Radio Frequency
Integrated Circuits (RFIC) Symposium Digest of Papers, June
2004 |
| [4] |
C. Menolfi, T. Toifl, M. Ruegg, R. Reutemann,
P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz, "A
25Gb/s PAM4 transmitter in 90nm CMOS SOI", International
Solid-State Circuits Conference (ISSCC) 2005, Digest of Technical
Papers, Feb. 2005 |
| [5] |
M. Kossel, P. Buchmann, C. Menolfi, T. Morf,
M. Schmatz, T. Toifl, J. Weiss, "Low-jitter 10 GHz multiphase
PLL in 90 nm CMOS", International Solid-State Circuits
Conference (ISSCC) 2005, Digest of Technical Papers, Feb. 2005 |
| [6] |
T. Morf , C. Menolfi, T. Toifl, C. Kromer, G.
Sialm, M. Kossel, J. Weiss, "Electrical and Optical Transceivers
for Short-Range Data Communication, Fabricated in VLSI 90 nm
Bulk and SOI CMOS Technology", proc. of IEEE Compound Semiconductor
IC Symposium CSICS Palm Springs, CA, USA, Oct. 30-Nov. 2. 2005 |
| [7] |
C. Kromer, G. Sialm, C. Berger, T. Morf, M. Schmatz,
F. Ellinger, D. Erni, G. Bona, H. Jäckel, "A 100-mW
4x10 Gb/s transceiver in 80-nm CMOS for high-density optical
interconnects", IEEE Journal of Solid-State Circuits, Volume
40, Issue 12, Dec. 2005, pp. 2667-2679 |
| [8] |
T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann,
P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz, "A
0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL
with 360° digitally programmable phase shift for 10-Gb/s
serial links", IEEE Journal of Solid-State Circuits, Volume
40, Issue 12, Dec. 2005, pp. 2700-2712 |
| [9] |
J. Weiss, M. Kossel, C. Menolfi, T. Morf, M.
Schmatz, T. Toifl, H. Jäckel, "A DC-to-44-GHz 19dB
Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement",
International Solid-State Circuits Conference (ISSCC) 2006,
Digest of Technical Papers, Feb. 2006 |
| [10] |
T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann,
P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz, "A
22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology", IEEE
Journal of Solid-State Circuits, Volume 41, Issue 4, April 2006,
pp. 954-965 |
| [11] |
C. Menolfi, T. Toifl, P. Buchmann, C. Hagleitner,
M. Kossel, T. Morf, M. Schmatz, "A 16Gb/s Source-Series
Terminated Transmitter in 65nm CMOS SOI", International
Solid-State Circuits Conference (ISSCC) 2007, Feb. 2007 |
| [12] |
T. Toifl, C. Menolfi, P. Buchmann, C. Hagleitner,
M. Kossel, T. Morf, M. Schmatz, "A 72mW 0.03mm2 Inductorless
40Gb/s CDR in 65nm SOI CMOS", International Solid-State
Circuits Conference (ISSCC) 2007, Feb. 2007 |
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Figure 1. A 20 Gbit/s, four-level pulse amplitude modulated (PAM-4) signal [4]. |
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Figure 2. Chip layout of high-bandwidth amplifier
circuit using integrated inductors [9]. |
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