CMOS link circuits

The continued shrinking of CMOS feature sizes allows us to build high-speed interconnect circuits at ever higher data rates. We explore new circuit architectures for transmitter and receiver circuits together with next-generation CMOS technology. The goal is to achieve the highest possible data rate at the lowest power consumption and smallest chip area.
Typical circuits include

• Transmitter/drivers circuits [4,6,7,11,15,17] with integrated feed-forward equalization (FFE)
• High-bandwidth input amplifiers/equalizer circuits [1,2,6,7,9]
• Receiver circuits with clock and data recovery (CDR) capability [6,8,10,12,14,16]
• Phase-locked loops (PLLs) for clock-generation. [3,5,8,13,14,18]
• Voltage regulators and circuits to cope with device variability [19].

Figure 1. A 20 Gb/s, four-level pulse amplitude modulated (PAM-4) signal [4].

Figure 2. Chip layout of high-bandwidth amplifier circuit using integrated inductors [9].