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Interconnects

Low-power CMOS drivers


Project overview

In the context of our CASE projects, a quad optical transceiver for low-power, high-density, short distance, fiber-optical data communication was designed, fabricated, packaged and tested. Each channel transmits 10 Gb/s over a multi-mode fiber, featuring a link margin of 5.2 dB at a BER=10^-12. The transmitter and receiver amplifying circuits are implemented in an 80 nm digital CMOS process. This work presented the highest serial data rate for CMOS transceiver arrays and the lowest power consumption per data rate (2.5 mW per Gigabit/s) reported at the time of publication [1].

 

 Selected publications

[1] C. Kromer, G. Sialm, C. Berger, T. Morf, M. L. Schmatz, F. Ellinger, D. Erni, G.-L. Bona, and H. Jackel, "A 100-Mw 4x10 Gb/S Transceiver in 80-Nm Cmos for High-Density Optical Interconnects," IEEE Journal of Solid-State Circuits, vol. 40, pp. 2667-2679, 2005.
Images, click to enlarge
Figure 1. Photo of transmitter assembly.
Photo of transmitter assembly
Figure 2. Photo of receiver assembly.
Photo of receiver assembly
Figure 3. Schematic view of single link.
Schematic view of single link.
Figure 4. 10 Gb/s eye diagram of single link.
10 Gb/s eye diagram of single link

 

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