As the throughput rates of next-generation servers approach several terabits per second, the chip-to-chip interconnects are becoming a limiting factor for overall system performance. Recognizing the importance of the "interconnect bottleneck", a dedicated research group is working on new technologies and advanced solutions in the field of low-power, high-speed, high-density chip-to-chip interconnects for next-generation servers and similar systems. The group's activities concentrate on
- architectural studies of mixed electrical/optical serial links,
- circuit design and simulation of key building blocks that optimally fit the proposed architectures,
- characterization of board and cable interconnect wires,
- very high-frequency characterization and modeling of IBM's next-generation CMOS processes.
The group maintains a number of collaborations with internal and external partners, for example in the framework of two related KTI (Kommission für Technologie und Innovation) projects and CASE (Center for Advanced Silicon Electronics).