An important research topic is the design of RF circuits in advanced CMOS technologies for transmitting data from chip to chip over relatively short distances, maximizing the data rate while minimizing power consumption and cost. CMOS (complementary metal oxide semiconductor) is today's mainstream IC technology for digital circuits (such as microprocessors). It is the technology of choice because it is less costly than its rivals and can be readily integrated on the same chip with digital logic. Traditionally, the minimum feature size of transistors has constantly been decreasing with time following Moore’s law, leading to ever faster transistors and higher degrees of integration.
The focus of our work is on low-voltage, low-power circuit design in the most advanced CMOS and CMOS SOI technologies. The goal is to integrate a multitude of high-speed links on a single digital chip, thereby achieving multi-Terabits/s aggregate bandwidth at low power consumption and small chip area. Low power consumption is a key requirement for these circuits, because firstly, only a limited amount of heat generated by the chip can be conducted through the chip package. The lower the power consumption, the more digital logic can be integrated on the same chip. Secondly, the power consumption of the entire system (such as a high-end server) is limited by the affordable cooling capacity.
Although advanced CMOS technologies offer excellent high-frequency properties, analog design becomes difficult due to increased transistor matching uncertainty and very low supply voltages, which can be only overcome by innovative circuit design techniques. Various link architectures are evaluated. When a signal is sent over a line (e.g., a cable or a trace on a printed circuit board), it suffers attenuation, which increases with the signal frequency. Hence, if more bits are sent over a single trace, the signal spectrum is shifted towards higher frequencies, leading to a higher signal loss per bit. This attenuation in electrical lines is mainly caused by the "skin effect" and dielectric losses in the medium. In addition, reflections of the electrical wave caused by connectors and via stubs in the printed circuit boards further degrade the quality of the transmitted signal. As a consequence, equalization and coding techniques are key to achieve higher data rates. However, these techniques always imply increased complexity, which directly translates into higher power consumption and greater chip area. Hence we are looking into equalizer structures and coding techniques, which can be implemented with low power and a small chip area.
In addition to the design work, we also perform high-level simulation of clock-data-recovery (CDR) circuits including channel equalization methods in order to optimize the jitter (RJ+SJ) performance of the CDR at the receiver.
Experimental verification is done in setups of electro-optical links for serializer/deserializer (SERDES) applications. Off-the-shelf components are used for the trans-impedance amplifier (TIA) and the 2.5 and 3.125 Gb/s SERDES chips with 8b/10b coding. Vertical-cavity-surface-emitting lasers (VCSELs) and photodiodes (PDs) are mounted as bare-die chips on dedicated RF substrates. Parts of the electro-optical link are to be replaced by circuits designed in advanced CMOS technology from IBM. This technology enables the electro-optical link to operate above 10 Gb/s.
Some of our activities are also dedicated to the modeling of passive millimeter integrated circuit (MMIC) components by means of electromagnetic field solver simulation tools.