Measurement and verification techniques

CMOS technology

State-of-the-art CMOS field effect transistors (FETs) achieve high-frequency performance that, only a few years ago, was only realizable with high-tech microwave devices based on GaAs or InP. Developing a superior CMOS transistor, however, is not sufficient. Modern analog integrated circuits have to be simulated extensively before they can be fabricated. Such simulations require accurate device models. The models calculate not only the current–voltage characteristics of the device, but also its high-frequency characteristics currently up to 100 GHz.

We invented a new method for on-wafer calibrations that enables accurate device de-embedding at frequencies above 100 GHz. These de-embedded measurements can be used to generate highly accurate and compact CMOS RF device models for application in a circuit simulator.

Board interconnect

Even for short chip-to-chip or board-to-board links, the characteristics of the channel (printed circuit board, connectors, coaxial cable) exhibit significant loss for Gb/s signals. Printed circuit boards and connectors are the cause of large contributions to loss and signal distortion. Knowledge of the channel characteristics is essential for system and circuit designers.

For this reason, key components of the channel are being analyzed in our group. This work is performed partially in cooperation with internal and external partners. Our goal is to investigate the fundamental speed limits of wire-bound chip-to-chip interconnects.

Measurement of link performance

Some of the activities of the I/O link technology group are dedicated to the characterization of electrical and optical serial link setups. The system-level characterizations include jitter, channel-to-channel skew and crosstalk measurements. Jitter is one of the most important issues in high-speed serial links, hence accurate jitter measurements are mandatory for the performance evaluation of such link types. Based on recommendations of standardization committees [32,33], jitter measurements are performed using the so-called BERT scan technique. In a BERT scan, the bit error rate (BER) is measured, as the sampling point of time is swept between the two zero crossings of an eye diagram. The resulting curve is commonly known as jitter bathtub curve; it is fitted to a jitter model to determine the required jitter numbers. This method has the advantage that an extrapolation of the BER performance to very low BER values (that cannot be measured within the available amount of time) can easily be done by means of the extracted RJ and DJ jitter numbers. The above jitter measurement method has been implemented in measurement automation tools (LabVIEW, Visual-C++) and is frequently used for link performance measurements in our lab. An example of a bathtub curve fit is shown in Fig. 3.

The corresponding eye diagram of the 2.5 Gb/s data signal is depicted in Fig. 4. A typical measurement setup using IBM's ASICS SERDES testchips [34] interconnected by parallel optical devices (POD) is illustrated in Fig. 5. Such measurement setups require a high degree of measurement automation and, above all, high-end measurement equipment.