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Over the past years, we have been witnessing a deceleration in
the growth rate of silicon technology capabilities. Driven by the
power density and the limiting effects of miniaturization, the growth
curve of CPU speed has flattened dramatically. This has resulted
in increased scrutiny of the code that is executed in servers and
a strong desire to enhance the efficiency of those servers. As the
density of silicon is not–yet?–subject to a flattening of
the curve, the flattening of the CPU speed, while the density of
silicon continues to increase, will lead to multi-core chips. These
chips contain multiple cache-coherent CPU cores, which work together
to deliver the required computer capacity.
In parallel, virtualization techniques have emerged in recent years
to unleash the power of contemporary CPUs for multiple applications,
and to isolate these applications from each other to achieve resiliency.
Extending virtualization to I/O requires a rethinking of the typical
PC server, bus-based, PCI type of I/O. Bus systems suffer from single
point of failure and will eventually be replaced by switch-based
systems, which will improve both the resiliency and the throughput
of the overall I/O system. Further scrutiny of the cycles spent
on the main CPU complex is likely to result in the observation that
the fairly "unproductive" (from an application point of
view) I/O cycles for controlling I/O hardware will be pushed out
of the application CPUs into the I/O subsystem, until eventually
complete network communication stacks, or even file-system handling,
will be offloaded into specific, embedded CPUs closer to network
or storage systems. In the past, cores designed especially for particular
functions were often not economically viable because, by the time
they were designed and programmed, general-purpose processors had
reached the capacity to address the task at the same speed. In the
near future, however, we expect special cores, such as for I/O and
XML processing, to become commonplace. Achieving cache-coherency
of such I/O cores is expected to be highly interesting, as this
can significantly reduce overhead caused by task switching and cache
misses for executing I/O operations in the same CPU.
Accordingly, our work concentrates on developing technology and
I/O concepts for IBM Systems and Technology group products. In particular
we focus on components for switched I/O and cluster systems, special
engines for I/O acceleration, and efficient architectures for multi-core
processor chips and systems.
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