Prizma-EP (IBM Power Packet Routing Switch 64G)
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The Prizma-EP (IBM PowerPRS 64G) is one of a family of second-generation switching devices designed for high-performance, nonblocking, fixed-length packet switching. This device is a single-chip switch element which exploits the performance advantage of the shared-output queuing structure and from which larger, self-routing single-stage or multi-stage switch fabrics can be constructed in a modular way. Prizma-EP is a 32x32@2Gb/s per port switching element, which enables the development of scalable switch fabrics with an aggregate bandwidth of 64 to 512 Gb/s. Internal and external speed expansion, port expansion, and port-paralleling configurations provide options for scaling the combination of port speed and the number of ports.

Prizma-EP builds on the Prizma packet routing switch architecture developed at IBM's Research Laboratory in the past decade [9]. The key features of the Prizma switch architecture are very high performance achieved by a strict separation of control and data paths, efficient queuing algorithms, and very large-scale integration on a single chip. This provides a unique level of flexibility, enabling multiple chips to be combined in many ways to build a broad range of communication nodes.

Whereas the initial Prizma switch architecture relied solely on output buffering (using a "shared memory" switch chip), the current architecture combines virtual-output queuing and output buffering [15]. This gives the switch its very high performance, independent of packet size.

Prizma-Related Publications

[1] H. Ahmadi, W.E. Denzel, C.A. Murphy, and  E. Port, “A high-performance switch fabric for integrated circuit and packet switching,” Int. Journal of Digital and Analog Cabled Systems, vol. 2, no. 4, 1989, pp. 277-287.
[2] I. Iliadis and W.E. Denzel, “Performance of packet switches with input and output queueing,” in Proc. ICC ’90, Apr. 1990, pp. 747-753.
[3] I. Iliadis, “Head of the line arbitration of packet switches with input and output queueing,” in Proc. IFIP TC6 Fourth International Conference on Data Communication Systems and their Performance, Barcelona, Spain, 1990, pp. 129-142.
[4] I. Iliadis, “Head of the line arbitration of packet switches with combined input and output queueing,” Int. J. Digital and Analog Commun. Syst., vol. 4, 1991, pp. 181-190.
[5] I. Iliadis, “Performance of a packet switch with shared buffer and input queueing,” in Proc. Teletraffic and Datatraffic in a Period of Change, ITC-13, 1991, pp. 911-916.
[6] A.P.J. Engbersen, “Multicast/broadcast mechanism for a shared buffer packet switch,” IBM Technical Disclosure Bulletin, vol. 34, no. 10a, Mar. 1992, pp. 464-465.
[7] I. Iliadis, “Synchronous versus asynchronous operation of a packet switch with combined input and output queuing,” Performance Evaluation 16, 1992, pp. 241-250.
[8] I. Iliadis, “Performance of a packet switch with input and output queuing under unbalanced traffic,” in Proc. IEEE INFOCOM ’92, May 6-8, 1992, pp. 743-752.
[9] W.E. Denzel, A.P.J. Engbersen, I. Iliadis, and G. Karlsson, “A highly modular packet switch for Gb/s rates,” in Proc. XIV International Switching Symposium, Yokohama, Oct. 25-30, 1992, pp. 237-240.
[10] I. Iliadis and W.E. Denzel, “Analysis of packet switches with input and output queuing,” IEEE Trans. Commun., vol. 41, no. 5, May 1993, pp. 731-740.
[11] W.E. Denzel, A.P.J. Engbersen, and I. Iliadis, “A flexible shared-buffer switch for ATM at Gb/s rates,” Computer Networks and ISDN Systems, vol.27, no. 4, Jan. 1995, pp. 611-624.

[12] M. Colmant, R. Luijten, “A single-chip, lossless 16 x 16 switch fabric with 28 Gb/s throughput,” IBM Research Report, RZ 3087, Dec. 1998.

[13] C. Minkenberg, T. Engbersen and M. Colmant, “A robust switch architecture for bursty traffic,” in Proc. Int. Zurich Seminar on Broadband Commun. IZS 2000, Zurich, Switzerland, Feb. 15-17, 2000, pp. 207-214.
[14] C. Minkenberg, “Integrating unicast and multicast traffic scheduling in a combined input- and output-queued packet-switching system,” in Proc. ICCCN 2000, Las Vegas, NV, Oct. 2000, pp. 127-234.
[15] C. Minkenberg and T. Engbersen, “A combined input and output queued packet-switched system based on PRIZMA switch-on-a-chip technology,” IEEE Commun. Mag., vol. 38, no. 12, Dec. 2000, pp. 70-77.
[16] R. Luijten, A. Engbersen, and C. Minkenberg, “Shared memory switching + virtual output queuing: a robust and scalable switch,” in Proc. ISCAS 2001, Sydney, Australia, May 6-9, 2001, vol. IV, pp. 274-277.

[17] F. Abel, "Design and verification methodology of modern high-speed switches", in Proc. of the third edidtion of Sophia Antipolis MicroElectronis forum, SAME 2000, pp. 30-38. Sophia Antipolis, France, Oct. 25-26, 2000.
[18]  A.P.J Engbersen, "Prizma switch technology," IBM Journal of Research and Development, vol. 47, no. 2/3, March/May 2003, pp. 195-209.

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