Oskar Mencer

Oskar Mencer

 Department of Computing 

Imperial College London 

 http://www.doc.ic.ac.uk/~oskar/

 

 

BIO:

Prior to founding Maxeler, Oskar was Member of Technical Staff at the Computing Sciences Center at Bell Labs in Murray Hill, leading the effort in "Stream Computing". He joined Bell Labs after receiving a PhD from Stanford University. Besides driving Maximum Performance Computing (MPC) at Maxeler, Oskar was Consulting Professor in Geophysics at Stanford University and he is also affiliated with the Computing Department at Imperial College London, having received two Best Paper Awards, an Imperial College Research Excellence Award in 2007 and a Special Award from Com.sult in 2012 for "revolutionising the world of computers".

 

Computing in Space

As the number of on-die transistors continues to grow, new computing models are needed to utilize this growing compute capacity despite a clock-frequency scaling wall, and relatively sluggish improvements in I/O bandwidth. The spatial compute and programming model, as introduced by the OpenSPL [1] specification, provides a method for taking advantage of compute capacity offered by current and trending hardware technology. With spatial computing, compute processing units are laid out in space (either physically or conceptually) and connected by flows of data. The result of this approach is compute implementations which are naturally highly-parallel and thus very effectively use modern transistor-rich hardware.

In this talk, I will describe both the spatial computing model and a practical realization of the OpenSPL specification: Multiscale Dataflow Engines. Multiscale Dataflow Engines are a platform which directly implements the spatial computing model in hardware while at the same time supporting tight integration with conventional CPU-based compute resources [2].

[1] www.openspl.org

[2] M. J. Flynn, O. Mencer, V. Milutinovic, G. Rakocevic, P. Stenstrom, R. Trobec, M. Valero: "Moving from Petaflops to Petadata", Communications of the ACM, May 2013

 

 

Jeff Stuecheli

Jeff Stuecheli

 Systems and Technology Group 

IBM 

 

 

BIO:

Dr. Stuecheli is a Senior Technical Staff Member in the Systems and Technology Group. He works in the area of server hardware architecture. His most recent work includes advanced memory architectures, cache coherence, and accelerator design. He has contributed to the development of numerous IBM products in the POWER architecture family, most recently the POWER8 design. He has been appointed an IBM Master Inventor, authoring some 100 patents. He received a B.S., M.S., and Ph.D. degrees from The University of Texas Austin in Electrical Engineering.

 

Open Innovation with POWER8

IBM introduces POWER8, the first generation of systems built with open innovation to put data to work; systems designed for big data, optimized to deliver superior cloud economics and an open innovation platform at the heart of the open collaborative community revolutionizing the way IT is created and consumed.

The POWER8 systems provide for a compelling combination of general purpose computing capability combined with the ability attach accelerators. This connection is made with CAPI (Coherent Accelerator Processor Interface), which enable PCIe devices to communicate with CPU cores as full peers using shared memory constructs.

 

 

Onur Mutlu

Onur Mutlu

 Electrical and Computer Engineering Department 

Carnegie Mellon University 

 http://users.ece.cmu.edu/~omutlu/

BIO:

Onur Mutlu is the Dr. William D. and Nancy W. Strecker Early Career Professor at Carnegie Mellon University. His broader research interests are in computer architecture and systems, especially in the interactions between languages, operating systems, compilers, and microarchitecture. He enjoys teaching and researching problems in computer architecture, including problems related to the design of memory systems, multi-core architectures, and scalable and efficient systems. He obtained his PhD and MS in ECE from the University of Texas at Austin (2006) and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. Prior to Carnegie Mellon, he worked at Microsoft Research (2006-2009), Intel Corporation, and Advanced Micro Devices. He was a recipient of the IEEE Computer Society Young Computer Architect Award, CMU College of Engineering George Tallman Ladd Research Award, Intel Early Career Faculty Honor Award, IBM Faculty Partnership Awards, HP Innovation Research Program Award, best paper awards at ASPLOS, VTS and ICCD, and a number of "computer architecture top pick" paper selections by the IEEE Micro magazine.

 

Rethinking Memory System Design for Data-Intensive Computing

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques.

In this talk, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we discuss three key solution directions: 1) enabling new memory architectures, functions, interfaces, and better integration of the memory and the rest of the system through, 2) designing a memory system that intelligently employs multiple memory technologies and coordinates memory and storage management using non-volatile memory technologies, 3) providing predictable performance and QoS to applications sharing the memory/storage system. We will discuss the specialization of the memory system as a means to enable better system scaling and discuss the use of memory as "yet another accelerator" in the system. If time permits, we may also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory.

An accompanying recent short paper can be found here.