A PDF version of the program can be downloaded from here.

 

Regular papers presentations: 20 mins + 5 mins Q&A

Short papers presentations: 10 mins

 

Wednesday

 

09:00 – 09:30

 

 

Opening Remarks

 

 

09:30 – 10:30

 

Keynote 1

Oskar Mencer:    Computing in Space
Presentation

 

 

10:30 – 11:00

 

 

Break

 

 

11:00 – 12:50

 

Session 1: Hardware Accelerators I

 

Regular papers

 

Resource-Efficient Regular Expression Matching Architecture for Text Analytics 
Kubilay Atasu 
Presentation

 

Map-Reduce Processing of K-means Algorithm with FPGA-accelerated Computer Cluster 
Yuk-Ming Choi and Hayden Kwok-Hay So
Presentation

 

Scalable SVD Unit for Fast Processing of Large LSE Problems on FPGAs 
Iñaki Bildosola, Unai Martinez-Corral and Koldo Basterretxea
Presentation

 

Short papers

 

SIR10US: A Tightly-Coupled Elliptic-Curve Cryptography Co-Processor for the OpenRISC 
Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim and Hubert Kaeslin

Presentation

 

Customizable Coarse-grained Energy-efficient Reconfigurable Packet Processing Architecture
Mohammad Badawi, Ahmed Hemani and Zhonghai Lu

 

Low Latency FPGA Acceleration of Market Data Feed Arbitration
Stewart Denholm, Hiroaki Inoue, Takashi Takenaka and Wayne Luk

Presentation

 

12:50 – 14:20

 

 

Lunch Break

 

 

14:20 – 15:30

 

Session 2: Computer Arithmetic

 

Regular papers

 

Sum-of-Product Architectures Computing Just Right 
Florent de Dinechin, Albdelbassat Massouri and Matei Istoan
Presentation

 

Pipelined Modular Multiplier Supporting Multiple Standard Prime Fields 
Hamad Alrimeih and Daler Rakhmatov
Presentation

 

Short papers

 

RNS Modular Multiplication through Reduced Base Extensions 
Karim Bigou and Arnaud Tisserand
Presentation

 

On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration 
Mioara Joldes, Jean-Michel Muller and Valentina Popescu
Presentation

 

 

15:30 – 16:30

 

 

Poster Session I Break

 

Polar Baseband Receiver for Low-End WLAN
Amro Altamimi, Daler Rakhmatov and Michael McGuire

 

Design of a 2D graphics front-end rendering processor
Yun-Nan Chang and Ting-Chi Tong

 

Performance Modeling of Virtualized Custom Logic Computations
Michael Hall and Roger Chamberlain

 

HICore1: "Safety on a Chip" Turnkey Solution for Industrial Control
Ali Hayek

 

A Reconfigurable Network-on-chip for Heterogeneous Many-core CMPs in the Dark Silicon Era
Mehdi Modarressi and Hamid Sarbazi-Azad

 

Randomized Windows for a Secure Crypto-Processor on Elliptic Curves
Simon Pontié and Paolo Maistri

 

Virtual semi-concurrent self-checking for heterogeneous MPSoC architectures
Mariagiovanna Sami and Gianluca Palermo

 

Distributed Synchronization for Message-passing based Embedded Multiprocessors
Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda and Guanyu Zhu

 

16:30 – 18:00

 

Session 3: Performance and Power Analysis

 

Regular papers

 

Performance Modeling for Highly-threaded Many-core GPUs 
Lin Ma, Roger Chamberlain and Kunal Agrawal
Presentation

 

Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system
Heiner Giefers, Raphael Polig and Christoph Hagleitner
Presentation

 

Coordinated and Adaptive Power Gating and Dynamic Voltage Scaling for Energy Minimization 
Nathaniel Conos, Saro Meguerdichian and Miodrag Potkonjak
Presentation

 

Short papers

 

A Case Against Small Data Types 
Ahmad Lashgar and Amirali Baniasadi
Presentation

 

Thursday

 

09:00 – 09:30

 

 

Announcements, Best Paper Awards, Introduction to ASAP 2015

 

 

09:30 – 10:30

 

Keynote 2

Jeff Stuecheli:    Open Innovation with POWER8
Presentation

 

 

10:30 – 11:00

 

 

Break

 

 

11:00 – 12:50

 

Session 4: Architectures I

 

Regular papers

 

He-P2012: Architectural Heterogeneity Exploration on a Scalable Many-Core Platform 
Francesco Conti, Chuck Pilkington, Andrea Marongiu and Luca Benini
Presentation

 

Function-Level Processor (FLP): Raising Efficiency by Operating at Function Granularity for Market-Oriented MPSoCs 
Hamed Tabkhi, Robert Bushey and Gunar Schirner
Presentation

 

Design of an Accelerator-Rich Architecture by Integrating Multiple Heterogeneous Coarse Grain Reconfigurable Arrays over a Network-on-Chip 
Waqar Hussain, Roberto Airoldi, Henry Hoffmann, Tapani Ahonen and Jari Nurmi
Presentation

 

Fault-tolerant on-chip networking through adaptive routing and dynamic partial reconfiguration 
Taimour Wehbe and Xiaofang Maggie Wang

 

Short papers

 

Secure Interrupts on low-end microcontrollers 
Ruan de Clercq, Dries Schellekens, Frank Piessens and Ingrid Verbauwhede

Presentation

 

 

12:50 – 14:20

 

Lunch Break

 

 

14:20 – 15:30

 

Session 5: Programming 

 

Regular papers

 

On the Portability of OpenCL Dwarfs on Fixed and Reconfigurable Parallel Platforms 
Konstantinos Krommydas, Wu-Chun Feng, Muhsen Owaida, Christos D. Antonopoulos and Nikolaos Bellas
Presentation

 

Evaluating Orthogonality between Application Auto-Tuning and Run-Time Resource Management for Adaptive OpenCL Applications 
Edoardo Paone, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano and Davide Gadioli
Presentation

 

Short papers

 

Efficient Application Mapping on CGRAs based on Backward Simultaneous Scheduling/Binding and Dynamic Graph Transformations 
Thomas Peyret, Gwenole Corre, Mathieu Thevenin, Kevin Martin and Philippe Coussy
Presentation

 

Domain-Specific Augmentations for High-Level Synthesis 
Moritz Schmid, Alexandru Tanase, Vivek Singh Bhadouria, Frank Hannig, Jürgen Teich and Dibyendu Ghoshal
Presentation

 

 

 

15:30 – 16:30

 

 

Poster Session II Break

 

Virtual science on the move: interactive access to simulations on supercomputers
Junyi Han, Bruce D'Amora, Bob Danani, Adel Salhi and John Brooke

 

A Practical Network Intrusion Detection System for Inline FPGAs on 10GbE Network Adapters
Keerthan Jaic, Melissa Smith and Nilim Sarma

 

An Approach of Processor-Core Customization for Stencil Computation
Yanhua Li, Youhui Zhang, Jianfeng Yang, Wayne Luk, Guangwen Yang and Weiming Zheng

 

SWAPHI: Smith-Waterman Protein Database Search on Xeon Phi Coprocessors
Yongchao Liu and Bertil Schmidt

 

A Scalable and Compact Systolic Architecture for Linear Solvers
Kevin S. H. Ong, Suhaib A. Fahmy and Keck-Voon Ling

 

Efficient and Scalable CGRA-based Implementation of Column-wise Givens Rotation
Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta Aponte, S K Nandy and Anupam Chattopadhyay

 

Bandwidth Compression of Multiple Numerical Data Streams for High Performance Custom Computing
Tomohiro Ueno, Ryo Ito, Kentaro Sano and Satoru Yamamoto

 

A Customized GPU Acceleration of the Princeton Ocean Model
Shizhen Xu, Xiaomeng Huang, Yan Zhang, Yong Hu and Guangwen Yang

 

16:30 – 18:00

 

Session 6: Hardware Accelerators II 

 

Regular papers

 

Pipelined Reconfigurable Accelerator for Ordinal Pattern Encoding 
Ce Guo, Wayne Luk and Stephen Weston
Presentation

 

Energy Efficient Canonical Huffman Encoding 
Janarbek Matai, Joo-Young Kim and Ryan Kastner
Presentation

 

Flexible Multistandard FEC Processor Design With ASIP Methodology 
Zhenzhi Wu and Dake Liu
Presentation

 

Short papers

 

Energy-Efficient Gear-Shift LDPC Decoders 
Kevin Cushon, Saied Hemati, Shie Mannor and Warren Gross

Presentation

 

Friday

 

09:00 – 09:10

 

 

Announcements

 

 

09:10 – 10:10

 

 

Keynote 3

Onur Mutlu:    Rethinking Memory System Design for Data-Intensive Computing
Presentation

 

 

10:10 – 11:00

 

Session 7: Memory

 

Regular Papers

 

Exploring DMA-assisted Prefetching strategies for Software Caches on Multicore Clusters 
Christian Pinto and Luca Benini
Presentation

 

A Compression-based Morphable PCM Architecture for Improving Resistance Drift Tolerance 
Majid Jalili and Hamid Sarbazi-Azad
Presentation

 

11:00 – 11:30

 

 

Break

 

 

11:30 – 13:00

 

 

Session 8: Architectures II

 

Regular papers

 

PVMC: Programmable Vector Memory Controller 
Tassadaq Hussain, Oscar Palomar, Osman Unsal, Adrian Cristal, Eduard Ayguade and Mateo Valero 

 

Understanding the Design Space of DRAM-Optimized Hardware FFT Accelerators 
Berkin Akin, Franz Franchetti and James Hoe
Presentation

 

Quality-aware Video Decoding on Thermally-constrained MPSoC Platforms 
Deepak Gangadharan, Samarjit Chakraborty and Jürgen Teich
Presentation

 

Short papers

 

Combining Flexibility with Low Power: Dataflow and Widepipeline LDPC Decoding Engines in the Gbit/s Era 
Joao Andrade, Frederico Pratas, Gabriel Falcao, Vitor Silva and Leonel Sousa

Presentation