Master’s student, Spring Semester 2020

Application-optimized data convertors for computational memory

Ref. 2020_013

General thesis description

For decades, conventional computers based on von Neumann architecture have performed computations by repeatedly transferring data between their physically separate processing and memory units. As computation becomes increasingly data-centric and as scalability limits in terms of performance and power are being reached, alternative computing paradigms are needed in which computation and storage are collocated. A fascinating new approach is that of computational memory, where the physics of nanoscale memory devices is leveraged to perform certain computational tasks within the memory unit in a non-von Neumann manner.

Computational Memory (CM) is being applied to a variety of areas such as machine learning and signal processing. AT IBM Research – Zurich we have shown experimental demonstrations of this concept using up to a million phase-change memory (PCM) devices. Unsupervised learning of temporal correlations, solution of linear equations and deep neural network inference and training are the most prominent applications that stand to benefit from a CM-based data-flow architecture.

Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are extensively employed in CM to handle the crossing between the digital and analog domains, in which computationally expensive tasks, such as matrix–vector multiplications (MVM), are performed with O(1) complexity. Each conversion costs a certain amount of energy, and its precision can only be guaranteed up to the effective number of bits (ENOB) of the employed data converter.


The research focus will be on understanding the system-level requirements on ADC and DAC for optimal performance of deep neural network inference using CM. Furthermore, the effects of noise, nonlinearity and manufacturing tolerances will be examined and counter-measurements, such as periodic digital ADC recalibration and digital post-processing, will be evaluated with regard to effectivity and energy costs.


The ideal candidate should be proficient in digital design for ASICs and/or FPGAs using Verilog or VHDL. Theoretical understanding of deep neural network inference and training as well as practical experience with the related Python frameworks is required. Detailed knowledge of common ADC topologies and ADC performance characterization is recommended and can be acquired in the early phase of the project. A strong mathematical background and programming skills will be a significant bonus. Prior knowledge of emerging memory technologies such as phase-change memory is not necessary. This work involves interactions with several researchers focusing on various aspects of the project, and the thesis research will be carried out at IBM Research – Zurich.


IBM is committed to diversity at the workplace. With us you will find an open, multicultural environment. Excellent, flexible working arrangements enable all genders to strike the desired balance between their professional development and their personal lives.

How to apply

Candidates interested in this project should please contact .