Scope

The 687th WE-Heraeus Seminar on “Scalable Hardware Platforms for Quantum Computing” brings together leading quantum scientists from academia and industry concentrating on the three main potentially scalable quantum architectures — ion traps, spin qubits in quantum dots, and superconducting qubits. This interdisciplinary seminar will focus on the technical challenges and the ecosystem to be developed in order to achieve a scalable quantum computer.


Motivation

Quantum computers are currently in the spotlight of high-performance computing. The media and even some scientific publications suggest that it is simply a matter of wiring up sufficiently many qubits to produce quantum computers that can solve the most complex problems imaginable in the very near future. Indeed, enormous progress has been made regarding the number and control of qubits, materials, fabrication, integration, understanding of error sources, quantum algorithms etc. However, a closer look reveals that this interdisciplinary field still requires a great deal of innovation before an operational quantum computer can be built. The holy grail of quantum computing, a universal gate-based quantum computer, requires qubits with extremely low error rates and integrated error correction, e.g. via the “surface code,” but this calls for many thousands of physical qubits to define a single, error-free logical qubit. Although in isolated experiments the required low error rates have been shown in several different qubit platforms, it has not yet been unambiguously demonstrated that this type of error correction can in fact lower a quantum system’s error rate.

This deficit can be attributed primarily to the fact that all elements in the system must function equally well with the highest fidelity. In particular,

  • Two-qubit interactions must feature low error rates.
  • Qubits must be coupled with at least their adjacent neighbors. This requires that qubits can be controlled from a nonplanar direction to enable scaling to larger processors.
  • The calibration of the system must be exact, time-stable and fast.
  • It must be possible to manipulate and select qubits simultaneously and with high fidelity, which places high demands on the control electronics. For error correction, a fast logic process is required to correct any errors that may occur.
  • A software environment is needed to generate quantum circuits efficiently on a given hardware platform.

To meet these challenges, a better understanding of the physics of error sources is critical. This will require well-controlled experiments with some tens or hundreds of qubits on scalable qubit platforms. Moreover, we need realistic quantitative comparisons of various technologies and platforms, e.g. via the “quantum volume,” a metric to compare gate-based quantum computer hardware by calculating the product of the number of qubits and the number of possible error-free sequential gate operations. Computing this quantity for existing platforms makes it clear that scaling to 50–100 currently available qubits or more does not yield higher performance. This raises questions regarding the key innovations needed to improve existing systems, and how the nucleation of new ideas can be fostered.

Important dates

  • Submissions are closed
  • Notification of acceptance: 9 November 2018

Organizing committee

  • Prof. Dr. David DiVincenzo
    RWTH Aachen, Director, Theoretical Nanosciences, Forschungszentrum Juelich, Germany
  • Dr. Stefan Filipp
    IBM Research – Zurich, Switzerland
  • Dr. Andreas Fuhrer (contact)
    IBM Research – Zurich, Switzerland
  • Prof. Dr. Frank Wilhelm-Mauch
    Universität des Saarlandes, Saarbrücken, Germany

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