Overview

“Maximizing I/O band­width at min­i­mum pow­er con­sump­tion is a key ena­bler for cog­ni­tive sys­tems”

—Marcel Kossel, IBM scientist

An important research topic is the design of RF circuits in advanced CMOS technologies for transmitting data from chip to chip over relatively short distances, maximizing the data rate while minimizing power consumption and cost.

CMOS (complementary metal oxide semiconductor) is today’s mainstream IC technology for digital circuits such as microprocessors. It is the technology of choice because it is less costly than its rivals and can be readily integrated on the same chip with digital logic.

Traditionally, the minimum feature size of transistors has constantly been decreasing with time following Moore’s Law, leading to ever faster transistors and higher degrees of integration.

Our focus

The focus of our work is on low-voltage, low-power circuit design in the most advanced CMOS and CMOS SOI technologies.

The goal is to integrate a multitude of high-speed links on a single digital chip, thereby achieving multi-Terabits/s aggregate bandwidth at low power consumption and small chip area.

Low power consumption is a key requirement for these circuits, because firstly, only a limited amount of heat generated by the chip can be conducted through the chip package. The lower the power consumption, the more digital logic can be integrated on the same chip.

Secondly, the power consumption of the entire system, such as a high-end server, is limited by the affordable cooling capacity.

Link architectures

Although advanced CMOS technologies offer excellent high-frequency properties, analog design becomes difficult due to increased transistor matching uncertainty and very low supply voltages.

This can be only overcome by innovative circuit design techniques.

We are evaluating various link architectures. When a signal is sent over a line such as a cable or a trace on a printed circuit board, it suffers attenuation, which increases with the signal frequency.

Hence, if more bits are sent over a single trace, the signal spectrum is shifted towards higher frequencies, leading to a higher signal loss per bit.

Architecture

This attenuation in electrical lines is mainly caused by the “skin effect” and dielectric losses in the medium.

In addition, reflections of the electrical wave caused by connectors and via stubs in the printed circuit boards further degrade the quality of the transmitted signal.

As a consequence, equalization and coding techniques are key to achieve higher data rates. However, these techniques always imply increased complexity, which directly translates into higher power consumption and greater chip area.

Hence we are looking into equalizer structures and coding techniques that can be implemented with low power and a small chip area.

CMOS link circuits

The continued shrinking of CMOS feature sizes allows us to build high-speed interconnect circuits at ever higher data rates. We are exploring new circuit architectures for transmitter and receiver circuits together with next-generation CMOS technology. Our goal is to achieve the highest possible data rate at the lowest power consumption and smallest chip area.

Typical circuits include

  • Transmitter/driver circuits with integrated feed-forward equalization (FFE)
  • DDR TX
  • Optical I/Os
  • High-bandwidth input amplifiers/equalizer circuits
  • Receiver circuits with clock and data recovery (CDR) capability
  • Phase-locked loops (PLLs) for clock generation
  • Voltage regulators and circuits to cope with device variability
  • Power converters
  • Digital I/O architectures
  • High-speed data converters (ADCs and DACs)
  • THz image detector

High-speed data converters

As data rates increase to 50 Gb/s and higher, more advanced modulation (e.g. PAM-4 and OFDM) require data converters operating at unprecedented speeds at low power consumption.

In this project, we explore the limits of data conversion with regard to conversion rate, power and chip area for high-speed I/O applications.

90GSs 8bit SAR ADC

90 GS/s 8-bit SAR ADC.

32GSs 6bit SAR ADC

Low-power 32 GS/s 6-bit SAR ADC.

Publications

  • 2018
    • C. Menolfi, M. Braendli, P.A. Francese, T. Morf, A. Cevrero, M. Kossel, L. Kull, D. Luu, I. Ozkaya, T. Toifl,
      “A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS,”
      ISSCC 2018.
    • I. Ozkaya, A. Cevrero, P.A. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, L. Kull, M. Kossel, D. Luu, M. Meghelli, Y. Leblebici, T. Toifl,
      “56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS,”
      ISSCC 2018.
    • L. Kull, D. Luu, C. Menolfi, M. Braendli, P.A. Francese, T. Morf, M. Kossel, A. Cevrero, I. Ozkaya, T. Toifl,
      “A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at Nyquist in 14nm CMOS FinFET,”
      ISSCC 2018.
    • A. Cevrero, I. Ozkaya, T. Morf, T. Toifl, M. Seifried, F. Ellinger, M. Khafaji, J. Pliva, R. Henker, N. Ledentsov, J.-R. Kropp, V. Shchukin, M. Zoldak, L. Halmo, I. Eddie, J. Turkiewicz,
      “4x40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR Lock Time in 14nm CMOS,”
      OFC 2018.
    • C. Aprile, A. Cevrero, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, L. Kull, I. Oezkaya, Y. Leblebici, V. Cevher, T. Toifl,
      “An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels,”
      IEEE Journal of Solid-State Circuits 53(3), 861-872, 2018.
    • I. Ozkaya, A. Cevrero, P.A. Francese, C. Menolfi, T. Morf, M. Brändli, D. M. Kuchta, L. Kull, C. W. Baks, J. E. Proesel, M. Kossel, D. Luu, B. G. Lee, F. E. Doany, M. Meghelli, Y. Leblebici, T. Toifl,
      “ A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET,”
      IEEE Journal of Solid-State Circuits, 2018.
  • 2017
    • T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brändli, P.A. Francese,
      ”A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery,”
      IEEE Transactions on Power Electronics 32(1), 378-393, 2017.
    • T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brändli, P.A. Francese,
      “Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters,”
      IEEE Transactions on Power Electronics 32(1), 363-377, 2017.
    • A. Cevrero, I. Ozkaya, P.A. Francese, C. Menolfi, T. Morf, M. Brandli, D. Kuchta, L. Kull, J. Proesel, M. Kossel, D. Luu, B. Lee, F. Doany, M. Meghelli, Y. Leblebici, T. Toifl,
      “A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET,”
      ISSCC 2017 (paper accepted).
    • L. Kull, D. Luu, C. Menolfi, M. Braendli, P.A. Francese, T. Morf, M. Kossel, H. Yueksel, A. Cevrero, I. Ozkaya, T. Toifl,
      “10b 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET,”
      ISSCC 2017 (paper accepted).
    • E. Sacco, P.A. Francese, M. Braendli, C. Menolfi, T. Morf, A. Cevrero, I. Oezkaya, M. Kossel, H. Yueksel, D. Luu, G. Gielen, T. Toifl,
      “A 5Gb/s 7.1fJ/b/mm 8x Multi-Drop on-chip 10mm Data Link in 14nm FinFET at 0.5V,”
      VLSI Circuits Symposium 2017, Kyoto, Japan.
    • A. Cevero, I. Oezkaya, P.A. Francese, C. Menolfi, M. Braendli, T. Morf, D Kuchta, M. Kossel, L. Kull, D. Luu, J. Proesel, Y. Leblebici, T. Toifl,
      “A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET,”
      VLSI Circuits Symposium 2017, Kyoto, Japan.
    • D. Luu, L. Kull, T. Toifl, C. Menolfi, M. Braendli, P.A. Francese, T. Morf, M. Kossel, H. Yueksel, A. Cevrero, I. Oezkaya, Q. Huang,
      “A 12b 61dB SNDR 300MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14nm CMOS FinFET,”
      VLSI Circuits Symposium 2017, Kyoto, Japan.
    • G. Gangasani, J.F. Bulzacchelli, M. Wielgos, W. Kelly, V. Sharma, A. Prati, G. Cervelli, D. Gardellini, M. Baecher, M. Shannon, T. Beukema, J. Garlett, H.H. Xu, T. Toifl, M. Meghelli, J. Ewen and D. Storaska,
      “A 28.05Gb/s Transceiver Using Quarter-Rate Triple-Speculation Hybrid-DFE Receiver with Calibrated Sampling Phases in 32nm CMOS,”
      VLSI Circuits Symposium 2017, Kyoto, Japan.
    • H. Yueksel, G. Cherubini, R. Cideciyan, A. Burg, T. Toifl,
      “Design Considerations on Sliding-Block Viterbi Detectors for High-Speed Data Transmission,”
      2016 9th International Conference on Signal Processing and Communication Systems (ICSPCS).
    • T. Toifl, A. Cevrero, I. Özkaya, P.A. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, M. Brändli, T. Morf,
      “Ultra-low Power 56Gb/s VCSEL-based Optical Links,”
      CMOSET 2017, Warsaw, Poland. (invited talk).
    • M. Kossel, C. Menolfi, P.A. Francese, L. Kull, T. Morf, T. Toifl, M. Braendli, A. Cevrero, D. Luu, Danny, I. Oezkaya, H. Yueksel,
      “DDR4 Transmitter with AC-Boost Equalization and Wide-band Voltage Regulators for Thin-Oxide Protection in 14-nm SOI CMOS Technology,”
      European Solid State Circuits Conference (ESSCIRC), 2017.
    • D. Luu, L. Kull, T. Toifl, C. Menolfi, M. Braendli, P.A. Francese, T. Morf, M. Kossel, H. Yueksel, A. Cevrero, I. Oezkaya, Q. Huang,
      “Background Calibration Using Noisy Reference ADC for a 12b 600MS/s 2×TI SAR ADC in 14nm CMOS FinFET,”
      European Solid State Circuits Conference (ESSCIRC), 2017.
    • R. Henker, T. Toifl, A. Cevrero, I. Oezkaya, M. Georgiades, M. Khafaji, J. Pliva, F. Ellinger,
      “Adaptive high-speed and ultra-low power optical interconnect for data center communications,”
      19th International Conference on Transparent Optical Networks (ICTON) 2017 (invited).
    • T. Morf, M. Seifried, A. Cevrero, I. Oezkaya, C. Menolfi, D. Kuchta, M. Kossel, P.A. Francese, L. Kull, J. Kropp, T. Toifl,
      “VCSEL-based optical links in burst-mode slow optical power ramp-up and how to achieve ultra-short wake-up times,”
      IET Electronics Letters 53(19), 2017.
    • A. Sebastian, T. Tuma, N. Papandreou, M. Le Gallo-Bourdeau, L. Kull, T. Parnell, E. Eleftheriou,
      “Temporal Correlation Detection Using Computational Phase-Change Memory,”
      Nature Communications, 2017.
    • I. Ozkaya, A. Cevrero, P.A. Francese, C. Menolfi, T. Morf, M. Brändli, D. M. Kuchta, L. Kull, C. W. Baks, J. E. Proesel, M. Kossel, D. Luu, B. G. Lee, F. E. Doany, M. Meghelli, Y. Leblebici, T. Toifl,
      “A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET,”
      IEEE Journal of Solid-State Circuits 52(12), 3458-3473, 2017.
  • 2016
    • H. Yüksel, M. Braendli, A. Burg, G. Cherubini, R.D. Cideciyan, P.A. Francese, S. Furrer, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, T. Toifl,”
      A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS,”
      Proc. 42nd European Solid-State Circuits Conference “ESSCIRC,”
      pp. 309-312, 2016.
    • P.A. Francese, M. Braendli, C. Menolfi, M. Kossel, T. Morf, L. Kull, A. Cevrero, H. Yüksel, I. Özkaya, D. Luu, T. Toifl,
      “A 30Gb/s 0.8pJ/b 14nm FinFET Receiver Data-Path,”
      Proc. International Solid-State Circuits Conference “ISSCC 2016,”
      San Francisco, USA, pp. 408-409.
    • S. Rylov, T. Beukema, Z. Toprak-Deniz, T. Toifl, Y. Liu, A. Agrawal, P. Buchmann, A. Rylyakov, M. Beakes, B. Parker, M. Meghelli,
      “A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI,”
      Proc. International Solid-State Circuits Conference “ISSCC 2016,”
      San Francisco, USA.
    • L. Kull, D. Luu, P.A. Francese, C. Menolfi, M. Braendli, M.A. Kossel, T. Morf, A. Cevrero, I. Özkaya, H. Yüksel, T. Toifl,
      “CMOS ADCs towards 100 GS/s and beyond,”
      Proc. 38th IEEE Compound Semiconductor IC (CSIC) Symposium, Austin, TX, 2016.
    • T. Toifl, M. Braendli, A. Cevrero, P.A. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, I. Özkaya, H. Yüksel,
      “Design Considerations for 50G+ Backplane Links,”
      Proc. 42nd European Solid-State Circuits Conference “ESSCIRC,”
      pp. 477-482, 2016.
    • M.A. Kossel, M. Braendli, P.A. Francese, L. Kull, C. Menolfi, T. Morf, T. Toifl, A. Cevrero, D. Luu, I. Özkaya, H. Yüksel,
      “Feedback Delay Reduction of Tomlinson-Harashima Precoder in 14-nm CMOS via Pipelined MAC Units Operated Entirely with CSA Arithmetic,”
      IET Electronics Letters 52(23), 1906, 2016.
    • L. Kull, J. Pliva, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M.A. Kossel, T. Morf, T. Meyer Andersen, Y. Leblebici,
      “Implementation of Low-Power 6-8b 30-90 GS/s Time-Interleaved ADCs with Optimized Input Bandwidth in 32 nm CMOS,”
      IEEE Journal of Solid State Circuits 51(3), 636-648, 2016.
    • H. Yueksel,G. Cherubini, R. Cideciyan, S. Furrer, A. Burg, T. Toifl,
      “High-speed link with trellis-coded modulation and Reed-Solomon coding,”
      2016 IEEE Conference on Standards for Communications and Networking (CSCN).
  • 2015
    • L. Kull,
      “Low-Power CMOS ADCs for 100+Gb/s Wireline Communications,”
      IEEE International Solid-State Circuits Conference (ISSCC), Wireline Forum (invited) 2015.
    • P.A. Francese, T. Toifl, M. Braendli, C. Menolfi, M. Kossel, T. Morf,
      “Continuous-Time Linear Equalization with Programmable Active-Peaking Transistor Arrays in a 14nm FinFET 2mW/Gb/s16Gb/s 2-Tap Speculative DFE Receiver,”
      IEEE International Solid-State Circuits Conference (ISSCC), 2015.
    • T.M. Andersen, F. Krismer, J. W. Kolar, T. Toifl, C. Menolfi, L. Kull,
      “A Feedforward Controlled On-Chip Switched-Capacitor Voltage Regulator Delivering 10W in 32nm SOI CMOS,”
      IEEE International Solid-State Circuits Conference (ISSCC), 2015.
    • H. Yueksel, L. Kull, A. Burg, M. Braendli, P. Buchmann, P.A. Francese, C. Menolfi, M. Kossel, T. Morf, T.M. Andersen, D. Luu, T. Toifl,
      “A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS,”
      European Solid State Circuits Conference (ESSCIRC), 2015.
    • A. Cevrero, C. Aprile, P.A. Francese, U. Bapst, C. Menolfi, M. Braendli, M. Kossel, T. Morf, L. Kull, H. Yueksel, I. Oezkaya, Y. Leblebici, V. Cevher,T. Toifl,
      “A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS,”
      VLSI Circuits Symposium 2015, Kyoto, Japan.
    • L. Kull,
      “Challenges in Implementing High-Speed, Low Power ADCs in CMOS,”
      Optical Fiber Communications Conference and Exhibition (OFC), 2015 (invited).
    • L. Kull, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T.M. Andersen, Y. Leblebici,
      “Energy-Efficient High-Speed SAR ADCs in CMOS,”
      High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, pp. 45-63, Springer, 2015.
    • D. Corcos, N. Kaminski, D. Elad, T. Morf, U. Drechsler, L. Kull,
      “Antenna-Coupled THz Sensors on-Chip,”
      IEEE / Israel EMC Conference, 2015.
    • D. Corcos, N. Kaminski, E. Shumaker, O. Markish, D. Elad, T. Morf, U. Drechsler, W.T. Silatsa Saha, L. Kull, K. Wood, U.R. Pfeiffer, J. Grzyb,
      “Antenna-Coupled MOSFET Bolometers for Uncooled THz Sensing,”
      IEEE Transactions on Terahertz Science and Technology 5(6), 902-913, 2015.
  • 2014
    • T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, P.A. Francese,
      “A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS,”
      Twenty-Ninth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2014.
    • T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, P.A. Francese,
      “A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trenchcapacitors in 32nm SOI CMOS,”
      IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014.
    • L. Kull, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T.M. Andersen, Y. Leblebici,
      “A 90GS/s 8b667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS,”
      IEEE International Solid-State Circuits Conference (ISSCC), 2014.
    • T. Toifl,
      “Low-Power Equalization and CDR for 10-28Gb/s SerDes,”
      Wireline Forum of the IEEE International Solid-State Circuits Conference (ISSCC), 2014 (invited).
    • L. Kull, J. Pliva, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T.M. Andersen, Y. Leblebici,
      “A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS,”
      IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014.
    • M. Kossel, C. Menolfi, T. Toifl, P.A. Francese, M. Brandli, T. Morf, L. Kull, T.M. Andersen, H. Yueksel,
      “A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI,”
      40th European Solid State Circuits Conference (ESSCIRC), 2014.
    • P.A Francese, T. Toifl, M. Brandli, P. Buchmann, T. Morf, M. Kossel, C. Menolfi, L. Kull, T.M. Andersen, H. Yueksel,
      “A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS,”
      40th European Solid State Circuits Conference (ESSCIRC), 2014.
    • T. Toifl, P.Buchmann, T. Beukema, M. Beakes, M. Brandli, P.A Francese, C. Menolfi, M. Kossel, L. Kull, T. Morf,
      “A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os,”
      40th European Solid State Circuits Conference (ESSCIRC), 2014
  • 2013
    • L. Kull, T. Toifl, M. Schmatz, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Meyer Andersen, Y. Leblebici,
      “A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS,”
      IEEE Int’l Solid-States Circuits Conf. “ISSCC 2013,”
      San Francisco, USA.
    • L. Kull, T. Toifl, M. Schmatz1, P.A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Meyer Andersen, Y. Leblebici,
      “A 35mW8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOICMOS,”
      VLSI Circuits Symposium 2013, Kyoto, Japan.
    • M. Kossel, C. Menolfi, T. Toifl, P.A. Francese, M. Brändli, P. Buchmann, L. Kull, T. Meyer Andersen, T. Morf,
      “A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s Thin-Oxide DDR Transmitter with 1.9-to-7.6V/ns Clock-Feathering Slew-Rate Control in 22nm CMOS,”
      IEEE Int'l Solid-States Circuits Conf. “ISSCC 2013,”
      San Francisco, USA.
    • T.M. Andersen, F. Krismer, J.W. Kolar, T. Toifl, C. Menolfi, L. Kull, T. Morf, M. Kossel, M. Brandli, P. Buchmann, P.A. Francese,“A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS,”
      Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2013.
    • M.A. Kossel, T. Toifl, P.A. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull, T. Meyer Andersen, T. Morf,
      “An 8Gb/s 1.5mW/Gb/s 8-Tap 6b NRZ/PAM-4 Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22nm CMOS,”
      IEEE Journal of Solid-State Circuits 48(12) 3268-3284, 2013.
    • T. Morf, B. Klein, M. Despont, U. Drechsler, L. Kull, D. Corcos, D. Elad, N. Kaminski, M. Braendli, C. Menolfi, M. Kossel, P.A. Francese, T. Toifl, D. Plettemeier,
      “Room-temperature THz imaging based on antenna-coupled MOSFET bolometer,”
      IEEE 26th International Conference on Micro Electro Mechanical Systems (MEMS), 2013.
  • 2012
    • T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, A. Prati, D. Gardellini, M. Brändli, M. Kossel, P. Buchmann, P.A. Francese, T. Morf,
      “A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS,”
      IEEE Journal of Solid-State Circuits 47(4) 897-910, 2012.
    • C. Menolfi, J. Hertle, T. Toifl, T. Morf, D. Gardellini, M. Braendli, P. Buchmann, M. Kossel,
      “A 28Gb/s source-series terminated TX in 32nm CMOS SOI,”
      IEEE Int'l Solid-States Circuits Conf. “ISSCC 2012,”
      San Francisco, USA.
    • J. Bulzacchelli, T. Beukema, D, Storaska, P. Hsieh, S. Rylov, D. Furrer, D. Gardellini, A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, K. Kelkar, H. Ainspan, W. Kelly, G. Ritter,J. Garlett, R. Callan, T. Toifl, D. Friedman,
      “A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology,”
      IEEE Int'l Solid-States Circuits Conf. “ISSCC 2012,”
      San Francisco, USA.
    • T. Toifl, M. Ruegg, R. Inti, C. Menolfi, M. Brandli, M. Kossel, P. Buchmann, P.A. Francese, T. Morf,
      “A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS,”
      Digest of Technical Papers VLSI Circuits Symposium 2012, Honolulu, USA.
  • 2011
    • T. Toifl,
      “Design Challenges, Latest Achievements and Future Directions of High-Speed I/Os,”
      IEEE Int'l Solid-States Circuits Conf. (ISSCC) 2011, Wireline Forum, San Francisco, USA, 2011 (invited).
    • R. Inti, A. Elshazly, B. Young, W. Yin, M. Kossel, T. Toifl, P.K. Hanumolu,
      “A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS,”
      IEEE Int'l Solid-States Circuits Conf. (ISSCC) 2011.
    • C. Menolfi, T. Toifl, M. Rueegg, M. Braendli, P. Buchmann, M. Kossel, T, Morf,
      “A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI,”
      IEEE Int'l Solid-States Circuits Conf. (ISSCC) 2011.
    • T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, A. Prati, D. Gardellini, M. Brändli, M. Kossel, P. Buchmann, P.A. Francese, T. Morf,
      “A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS,”
      Digest of Technical Papers,VLSI Circuits Symposium 2011, Kyoto, Japan.
    • R. Reutemann, M. Ruegg, F. Keyser, J. Bergkvist, D. Dreps, T. Toifl, M. Schmatz,
      “A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS,”
      IEEE Journal of Solid-State Circuits 45(12) 2850-2860, 2010.
  • 2009
    • M. Kossel, T. Morf, J. Weiss, P. Buchmann, C. Menolfi, T. Toifl, M. Schmatz,
      “LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS,”
      IEEE Journal of Solid-State Circuits 44(2) 436-449, 2009.
    • T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, M. Schmatz,
      “A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS,”
      IEEE Journal of Solid-State Circuits 44(2) 2901-2910, 2009.
    • M. Kossel, C. Menolfi, M. Braendli, P. Buchmann, T. Morf, T. Toifl, M. Schmatz,
      “Design of source-series-terminated transmitters with T-coils,”
      CMOS Emerging Technologies Workshop CMOSET, Sept. 23-25, 2009, Vancouver, Canada.
    • M. Kossel, T. Morf, P. Buchmann, M. Schmatz, C. Menolfi, T. Toifl,
      “Switched inductor with wide tuning range and small inductance step sizes,”
      IEEE Microwave and Wireless Components Letters (MWCL) 19, 515-517, Aug. 2009.
    • T. Toifl, C. Menolfi, M. Kossel, M. Braendli, T. Morf, P. Buchmann, M. Schmatz,
      “Low Power and Compact Transceivers for High-Speed Wireline Communications,”
      CMOS Emerging Technologies Workshop (CMOSET), Feb. 18-20, 2009, Banff, Canada.
  • 2008
    • T. Toifl,
      “Design Techniques for Ultra-Low Power and Compact Transceivers in CMOS,”
      Wireline Forum of the InternationalSolid-State Circuits Conference (ISSCC) 2008, Feb. 2008 (invited).
    • M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T. Toifl, M. Schmatz,
      “A T-coil Enhanced 8.5Gb/s High-swing Source-series-terminated Transmitter in 65nm Bulk CMOS,”
      International Solid-State Circuits Conf. (ISSCC) 2008, San Francisco.
    • G. von Bueren, L. Rodoni, A. Huber, R. Brun, D. Holzer, M. Schmatz, H. Jäckel,
      “6 to 40 Gb/s Quarter-rate CDR with Data-rate Selection in 90 nm Bulk CMOS,”
      European Solid-State Circuits Conference (ESSCIRC) 2008, Oct. 2008.
    • M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T. Toifl, M. Schmatz,”
      A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With <−16 dB Return Loss Over 10 GHz Bandwidth,”
      IEEE Journal of Solid-State Circuits 43(12), 2905-2920, 2008.
    • T. Toifl, C. Menolfi, P. Buchmann, M. Kossel, T. Morf, M. Schmatz,
      “A small-area voltage regulator with high-bandwidth supply-rejection using a regulated replica in 45nm CMOS SOI,”
      IEEE Asian Solid-State Circuits Conference, Fukuoka, Japan, Nov 2008.
    • C. Berger, L. Dellmann, P. Dill, F. Horst, B. Offrein, M. Schmatz, S. Oggioni, M. Spreafico, G. Macario,
      “Integration of Optical I/O with Organic Chip Packages,”
      in Photonics Packaging, Integration, and Interconnects VIII, edited by A.L. Glebov, R.T. Chen, Proc. SPIE, Vol. 6899, 689912 (2008). Proceedings Photonics West 2008, San Jose, CA, January 2008.
  • 2007
    • C. Menolfi, T. Toifl, P. Buchmann, C. Hagleitner, M. Kossel, T. Morf, M. Schmatz,
      “A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI,”
      International Solid-State Circuits Conference (ISSCC) 2007, Feb. 2007.
    • T. Toifl, C. Menolfi, P. Buchmann, C. Hagleitner, M. Kossel,T. Morf, M. Schmatz,
      “A 72mW 0.03mm2Inductorless 40Gb/s CDR in 65nm SOI CMOS,”
      International Solid-State Circuits Conference (ISSCC) 2007, Feb. 2007.
    • T. Morf, M. Kossel, J. Weiss, C. Menolfi, T. Toifl, G. von Bueren, P. Buchmann, M. Schmatz,
      “Wide Tuning Range LC-Oscillator in 65 nm SOI CMOS, Based on Switchable Secondary Inductor,”
      IET (IEE) Electron. Lett. 43(24) 1364-1365, 2007.
  • 2006
    • J. Weiss, M. Kossel, C. Menolfi, T. Morf, M. Schmatz, T. Toifl, H. Jäckel,
      “A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement,”
      International Solid-State Circuits Conference (ISSCC) 2006, Digest of Technical Papers, Feb. 2006.
    • T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz,
      “A 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology,”
      IEEE Journal of Solid-State Circuits 41(4) 954-965, 2006.
    • T. Lamprecht, F. Horst, R. Dangel, R. Beyeler, N. Meier, L. Dellmann, M. Gmür, C. Berger, and B. Offrein,
      “Passive Alignment of Optical Elements in a Printed Circuit Board,”
      56th Electronic Components and Technology Conference (ECTC 2006), San Diego, 2006.
    • T. Toifl, M. Schmatz, C. Menolfi,
      “Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components,”
      IEEE Transactions on Communications 54(9) 1554-1557, 2006.
  • 2005
    • C. Menolfi, T. Toifl, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz,
      “A 25Gb/s PAM4 transmitter in 90nm CMOS SOI,”
      International Solid-State Circuits Conference (ISSCC) 2005, Digest of Technical Papers, Feb. 2005.
    • M. Kossel, P. Buchmann, C. Menolfi, T. Morf, M. Schmatz, T. Toifl, J. Weiss,
      “Low-jitter 10 GHz multiphase PLL in 90 nm CMOS,”
      International Solid-State Circuits Conference (ISSCC) 2005, Digest of Technical Papers, Feb. 2000.
    • T. Morf, C. Menolfi, T. Toifl, C. Kromer, G. Sialm, M. Kossel, J. Weiss,
      “Electrical and Optical Transceivers for Short-Range Data Communication, Fabricated in VLSI90 nm Bulk and SOI CMOS Technology,”
      Proc. IEEE Compound Semiconductor IC Symposium CSICS, Palm Springs, USA, 2005.
    • C. Kromer, G. Sialm, C. Berger, T. Morf, M. Schmatz, F. Ellinger, D. Erni, G. Bona, H. Jäckel,
      “A 100-mW 4x10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects,”
      IEEE Journal of Solid-State Circuits 40(12) 2667-2679, 2005.
    • T. Toifl, C. Menolfi, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T. Morf, J. Weiss, M. Schmatz,
      “A 0.94-ps-RMS-jitter 0.016-mm22.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links,”
      IEEE Journal of Solid-State Circuits 40(12) 2700-2712, 2005.
    • L. Dellmann, T. Lamprecht, S. Oggioni, M.Witzig, R. Dangel, R. Beyeler, C. Berger, F. Horst, and B. Offrein,
      “Butt-Coupled Optoelectronic Modules for High-Speed Optical Interconnects,”
      Proc. CLEO/Europe-EQEC 2005, Munich, 2005.
    • B. Offrein, C. Berger, R. Beyeler, R. Dangel, L. Dellmann, F. Horst, T. Lamprecht, N. Meier, R. Budd, F. Libsch, and J. Kash,
      “Parallel optical interconnects in printed circuit boards,”
      Proc. SPIE, vol. 5990, pp. 117-125, 2005.
    • T. Morf, C. Menolfi, T. Toifl, C. Kromer, G. Sialm, M. Kossel, J. Weiss, P. Buchmann, C. Berger,and M. Schmatz,
      “Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology,”
      Compound Semiconductor Integrated Circuit Symposium, 2005. CSICS’05. IEEE, 2005.
  • 2004
    • C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Ellinger, D. Erni, H. Jäckel,
      “A low-power 20-GHz 52-dB transimpedance amplifier in 80-nm CMOS,”
      IEEE Journal of Solid-State Circuits 39(6) 885-894, 2004.
    • M. Kossel, T. Morf, W. Baumberger, A. Biber, C. Menolfi, T. Toifl, M. Schmatz,
      “A multiphase PLL for 10 Gb/s links in SOI CMOS technology,”
      Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers, June 2004.
    • G.-L. Bona, B. Offrein, U. Bapst, C. Berger, R. Beyeler, R. Budd, R. Dangel, L. Dellmann, F. Horst,
      “Characterization of parallel optical-interconnect waveguides integrated on a printed circuit board,”
      Proc. SPIE, vol. 5453, 2004.
    • C. Berger, U. Bapst, G.-L. Bona, R. Dangel, L. Dellmann, P. Dill, M.A. Kossel, T. Morf, B. Offrein, and M. L. Schmatz,
      “Design and implementation of an optical interconnect demonstrator with board-integrated waveguides and microlens coupling,”
      Biophotonics/Optical Interconnects and VLSI Photonics/WBM Microcavities, 2004 Digest of the LEOS Summer Topical Meetings, 2004.
    • R. Dangel, U. Bapst, C. Berger, R. Beyeler, L. Dellmann, F. Horst, B. Offrein, and G.-L. Bona,
      “Development of a low-cost low-loss polymer waveguide technology for parallel optical interconnect applications,”
      Biophotonics/Optical Interconnects and VLSI Photonics/WBM Microcavities, 2004 Digest of the LEOS Summer Topical Meetings, 2004.
  • 2003
    • C. Berger, M. Kossel, C. Menolfi, T. Morf, T. Toifl, and M. Schmatz,
      “High-density optical interconnects within large-scale systems,”
      Proc. SPIE, vol. 4942, pp. 222-235, 2003.
    • T. Toifl, C. Menolfi, M. Kossel, T. Morf, M. Schmatz,
      “A 23GHz differential amplifier with monolithically integrated T-coils in 0.09µm CMOS technology,”
      IEEE Microwave Symposium Technical Digest, Philadelphia, June 2003.