Investigation of novel materials for continued electronic chip miniaturization

Zurich, Switzerland, 21 September 2001—The ambitious goal of INVEST* is to develop the use of new materials at the core of microelectronic chips, which will be crucial for continued miniaturization well beyond the foreseeable limits of today's technology. The results are expected to increase the competitiveness of the European semiconductor industry and to solidify its position among the leaders in silicon integrated circuit and system innovation.

Size and performance of individual transistors on microelectronic chips depend to a large extent on a thin layer between the transistor gate and the semiconducting silicon. This layer must have dielectric properties, i.e. no current flows through the material but a charge is built up by applying an electrical field at the gate. The charge causes a conducting channel to be formed in the silicon below the layer, thus switching on the transistor. For the past three decades, dielectric layers have been made of silicon dioxide as a cornerstone of silicon-based integrated circuits.

The dielectric properties desired in transistors depend on the geometry of the structure, i.e. both area and thickness of the layer must be reduced proportionally with shrinking devices. Miniaturization now approaches a limit where the silicon-dioxide layer becomes too thin and risks losing its insulating properties, leading to a leakage current. A solution to this problem is offered by new materials having higher dielectric constants than silicon dioxide does, which will allow thicker layers at smaller lateral dimensions.

INVEST's primary objective is to introduce new gate materials based on metal oxides characterized by a high dielectric constant "k" (higher than 20) and a relatively large physical thickness (3 -10 nm). In contrast to the current efforts of the global semiconductor industry, which focus on short-term replacements for silicon dioxide, INVEST targets very high dielectric constant materials, which will be needed for the longer term. The general consensus is that this approach allows continuation of transistor downscaling, from today's minimum lateral dimensions of 130 nm to the range of 50 -100 nanometers.

First results achieved by experts who have now joined the consortium are very promising. Introduction of new materials into a well-established and cost-effective manufacturing process, however, poses a number of major challenges.

The INVEST project will address issues such as properties of materials and quality of interfaces, requirements for manufacturing equipment, transistor device performance and reliability, and process integration and compatibility with CMOS as today's predominant chip technology.

While current industry efforts concentrate on gate oxide materials grown by CVD (chemical vapor deposition), INVEST's research will focus on single crystalline, epitaxial layers grown directly on silicon with the so-called MBE technique (molecular beam epitaxy). The project team also plans to integrate an MBE growth step of high-k dielectrics into an 8-inch silicon-wafer processing line.

MBE has traditionally been deployed to manufacture devices based on so-called III-V compound semiconductors, such as gallium-arsenide. The INVEST team now hopes to extend MBE technology into mainstream silicon-based semiconductor processing. IBM Research - Zurich is expected to make a major contribution, based on its unique expertise in MBE growth of atomically precise thin films in various fields. The INVEST project is aimed at identifying potential materials within two years and, by the end of the three-year program, at acquiring essential knowledge about the suitability of high-k metal oxides for continued downscaling of CMOS technology in 2005 and beyond. The results are expected to strengthen the competitive edge of Europe, which already is a world leader in MBE, and to lead to commercialization of an innovative oxide-film production system.

* INVEST stands for "Integration of very high-k dielectrics with silicon CMOS technology". The project is funded by the European Commission's fifth framework program on Information Society Technologies (IST), and was launched in July 2001. The members are two semiconductor chip manufacturers (IBM, represented by its Zurich Research Laboratory, Switzerland; and Philips, represented by its research facility in Leuven, Belgium), two UHV equipment and component manufacturers (RIBER S.A, France; and Oxford Applied Research Ltd.,UK), an independent research center specializing in microelectronics process development (Interuniversitair Micro-Elektronica Centrum, Belgium) and four research and academic institutions promoting materials science and engineering (National Center for Scientific Research "Demokritos" — Institute of Materials Science, Greece; Max Planck-Institut Halle, Germany; Istituto Nazionale per la Fisica della Materia — Laboratorio MDM, Italy; and Clausthal University of Technology, Germany).