Thermal management roadmap

The thermal management of 3D chip stacks is perceived to be a limiting factor in dense system integration, given the increased volumetric power density and accumulation of thermal interfaces [1]. Hence, 3D integration will be a key driver for novel cooling solutions.

The industry will also exploit existing cooling solutions developed for single-die packages for 3D chip stack modules. For flip-chip packages, heat is removed through the die backside and is absorbed, for example in a liquid cold plate. A copper lid between the two materials typically provides mechanical protection for the chip (Figure 1 lid-attached).

3D inte­gra­tion will be a key driv­er for nov­el cool­ing solu­tions.

—IBM scientist Gerd Schlottig

Thermal coupling between solid elements is established by thermal interface materials (TIMs). The number of TIMs can be reduced from two to one by considering a lidless module with an integrated direct-attached cold plate, which involves a tradeoff between lower mechanical robustness but higher thermal performance (Figure 1 direct-attach). The embedding of microchannels into the back of the chip stack’s top die eliminates all TIMs in the thermal path, but requires leak-tight fluid interconnects from the system fluid loop to the silicon chip stack (Figure 1 embedded).

More disruptive options to overcome the thermal limits of 3D chip stacks are topology changes from single to dual-side and volumetric heat removal. Several studies have demonstrated approaches to enhance the thermal conductivity of organic substrates, while maintaining electrical functionality. This enables a second cold plate to be applied at the bottom of the lidded module (Figure 1 thermal laminate).

Dual-side heat removal can also be established by integrating fluid channels into a silicon interposer, while maintaining through-silicon-via (TSV) capability with sealing structures (Figure 1 convective interposer). The ultimate solution resulting in volumetric heat removal is to integrate microchannels between the active dies in the chip stack. This approach needs to deal with the high density of TSVs at pitches below 100 μm (Figure 1 interlayer).


Backside cooling evolution
Figure 1: Backside cooling evolution from lid-attached to direct-attached and ultimately to embedded convective cooling. Roadmap of disruptive cooling approaches, ranging from dual-side cooling, considering thermal laminates or convective interposers, to volumetric heat removal with integrated fluid channels between active dies [1].


Lid-integral silicon microchannel cold plate

Backside cooling considering a lid-integral cold plate topology allows one thermal interface to be eliminated, while still separating the coolant from the integrated circuit (IC) die [2]. The use of silicon as a cold plate material allows optimized microchannel fluid networks with the precision of microfabrication. In addition, matching the thermal expansion between the IC die and the cold plate improves heat conduction coupling between the two components.

To allow system access to the liquid-carrying silicon parts, the cold plates were integrated into injection-molded manifold lids. They support hierarchical fluid delivery networks and result in a split-flow with a reduced pressure drop, even for small hydraulic radii of the staggered fin arrays in silicon. Thermal resistances from cold plate base to coolant inlet of 13 mm2K/W at 30 kPa pressure drop have been reported (Figure 2).


Photograph of injection-molded manifold
Figure 2: a) Photograph of injection-molded manifold. b) SEM of a section of the cold plate with staggered micro-fins (200 μm pitch, 100 μm wide and 200 μm tall). c) Cross section of a CPU module including the silicon cold plate.


Dual-side liquid cooling by liquid cooled silicon interposer

A microchannel cold plate and an interposer with fluid channels is integrated on the back and front sides of a chip stack or a single die to establish dual-side convective heat removal (Figure 3) [3]. The manifold distributes and drains the coolant to and from the cold plate. Furthermore, a fluidic interconnection between the cold plate and the interposer feeds the coolant parallel to the cold plate to the interposer cavity. The electrical functionality of the interposer is provided by the integrated TSVs, allowing signaling and power delivery to the laminate by a land-grid-array socket (LGA). This cooling topology provides a 2× heat removal capability, while maintaining the electrical functionality.


Cross-sectional view of a module with dual-side colling topology
Figure 3: a) Cross-sectional view of a module with dual-side cooling topology. The thermal chip represents a chip stack or a single die. b) SEM of the interposer with microchannels containing the sealing-ring structures around the TSV pads to separate the coolant from the electrical interconnects.


Interlayer cooling — True volumetric scaling

Interlayer cooling is the only volumetric cooling solution that scales with the number of dies in the chip stack (Figure 4a) and hence enables extreme 3D integration. The vicinity of electrical interconnects to water coolant running through the chip stack fluid cavities requires specific sealing structures [4], such as rings. Two-phase dielectric cooling can mitigate this complexity [5]. However, structural integrity needs to be supported by the package even for high pressures (Figure 4b, c) [6].


Sketch of the interlayer cooling topology. b) Interlayer cooled module. c) SEM image cross section of an interlayer-cooled chip stack with embedded TSVs in the microchannel walls.
Figure 4: a) Sketch of the interlayer cooling topology. b) Interlayer cooled module. c) SEM image cross section of an interlayer-cooled chip stack with embedded TSVs in the microchannel walls.

Electro-thermal co-design is necessary in order to achieve a reliable chip stack design owing to the proximity of the coolant to the heat-generating transistors. Accordingly, detailed knowledge of the heat and mass transport in microchannel cavities is key and can be explored using microparticle image velocimetry and laser-induced fluorescence microscopy (Figure 5a). The derived correlations are used in compact thermal modeling solvers to derive the time domain temperature map in a chip stack. 3D-ICE and STEAM models were developed using this method for single and two-phase convective cooling in chip stacks, respectivley (Figure 5b, c) [7, 8].


a) Characterization of fluid temperatures in micro-pin fin arrays by laser-induced fluorescence. b) Compact thermal modeling considering temperature-dependent current courses to represent convection. c) Resulting temperature map considering interlayer cooling.
Figure 5: a) Characterization of fluid temperatures in micro-pin fin arrays by laser-induced fluorescence. b) Compact thermal modeling considering temperature-dependent current courses to represent convection. c) Resulting temperature map considering interlayer cooling.


Volumetric heat fluxes of up to 3.9 kW cm−3 were demonstrated experimentally for a three-tier stack with simple straight microchannels [4]. More sophisticated fluid cavities are under investigation and have the potential to improve heat removal performance. Accordingly, Figure 6a shows a sketch of an interlayer cooling roadmap considering a step-wise introduction of

i) heat transfer unit cell variation,
ii) modulation of heat transfer structures,
iii) fluid focusing by fluid networks,
iv) 4-port fluid delivery,

v) interlayer cooling adapted power map,
vi) temporal work-load allocation strategies and
vii) slip-flow by superhydrophobic surfaces.


a) Interlayer cooling roadmap indicating the trend towards more sophisticated fluid networks. b) Sam Palmisano (former IBM CEO) handing an interlayer-cooled mockup to German chancellor Angela Merkel at CeBit.
Figure 6: a) Interlayer cooling roadmap indicating the trend towards more sophisticated fluid networks. b) Sam Palmisano (former IBM CEO) handing an interlayer-cooled mockup to German chancellor Angela Merkel at CeBit.


References

[1] T. Brunschwiler, A. Sridhar, C. L. Ong, and G. Schlottig, “Benchmarking study on the thermal management landscape for 3D ICs: From back-side, to volumetric heat removal,” Journal of Electronic Packaging, 138(1), 2016.

[2] G. Schlottig, W. Escher, V. Khanna, T. Brunschwiler, et al., “Lid-integral cold-plate topology: Integration, performance, and reliability,” Journal of Electronic Packaging, 138 (1), 2016.

[3] T. Brunschwiler, O. Ozsun, G. Schlottig, et al., “Dual-side heat removal by micro-channel cold plate and silicon-interposer with embedded fluid channels,” Proc. 6th Electronic System-Integration Technology Conference (ESTC), Grenoble, France, pp. 1-6, 2016.

[4] T. Brunschwiler, B. Michel, S. Paredes, U. Drechsler, W. Cesar, G. Toeral, Y. Temiz, Y. Leblebici, “Validation of porous-media prediction of interlayer cooled 3D-chip stacks,” Proc. IEEE International Conference on 3D System Integration, 3DIC , San Francisco CA, p. 1-10, 2009.

[5] C. L. Ong, S. Paredes, A. Sridhar, B. Michel, T. Brunschwiler, “Radial hierarchical microfluidic evaporative cooling for 3-D integrated microprocessors,” Proc. 4th European Conference on Microfluidics, Limerick, 2014.

[6] Y. Madhour, B. Michel, et al., “Modeling of two-phase evaporative heat transfer in three-dimensional multicavity high performance microprocessor chip stacks,” Journal of Electronic Packaging, 136(2), 2014.

[7] A. Sridhar, M. Sabry, T. Brunschwiler, and D. Atienza, “3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling,” International Conference on Computer-Aided Design, San Jose CA, 2010.

[8] A. Sridhar, Y. Madhour, D. Atienza, T. Brunschwiler and J. Thome, “STEAM: A fast compact thermal model for two-phase cooling of integrated circuits,” 32nd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, 2013.


Ask the experts

Gerd Schlottig

Gerd Schlottig

IBM Research scientist

Arvind Sridhar

Arvind Sridhar

IBM Research scientist

Thomas Brunschwiler

Thomas Brunschwiler

IBM Research scientist

 


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