TASE

Figure 1. III–V crystal grows and expands into the predefined template until it fills the entire cavity.


TASE

Figure 2. Deposition of various III–V compounds on Si

Template-assisted selective epitaxy (TASE)

We have developed an epitaxial growth method to deposit III–V materials on Si, which results in good material quality and is compatible with CMOS processes.

In TASE, the III–V material is deposited selectively on a small (Si) seed crystal, which can be located on a Si or silicon-on-insulator (SOI) wafer. Continuing from this nucleation step, the III–V crystal grows further and expands into the predefined template until it fills the entire cavity. The process is illustrated in Fig. 1.

We have deposited various III–V compounds on Si as illustrated in Fig. 2 and processed the nanowires or platelets in state-of-the-art field effect transistors (FETs), heterojunction tunnel FETs.

We are continuing to develop the TASE process for electronic, optoelectronic and sensor applications, also within several European projects.

Ask the experts

Lukas Czornomaz

IBM Research scientist

Heinz Schmid

IBM Research scientist

Stephan Wirths

IBM Research scientist

Yannick Baumgartner

Yannick Baumgartner

IBM Research scientist


3D integration

For the realization of dense, hybridInGaAs/SiGe CMOS circuits on Si, which relies on standard CMOS fabrication process modules, we developed a novel selective growth technique of thin InGaAs platelets in empty oxide cavities by metal-organic chemical vapor deposition (MOCVD).

This tech­nol­ogy can be ex­tend­ed to many oth­er ap­pli­ca­tions than CMOS.

—Lukas Czornomaz
IBM Research scientist

3d integrationFirst, pFET active regions (mesas or fins) are formed by dry etching. Next, empty SiO2 cavities are formed with an access to the Si substrate acting as a crystalline seed. The empty cavities are then refilled in an InGaAs epitaxy step, where the growth direction is changed from vertical to lateral. This way, geometrical defect filtering in all directions is handled with minimal area penalty, whereas the lateral growth direction is used for defining nFET-active regions. This process, particularly well-suited for the density requirements of CMOS technology, is referred to as confined epitaxial lateral overgrowth (CELO) in [1]. It belongs to a family of template-assisted selective epitaxy techniques (TASE) reported for different geometries and materials in [2].

Using this technique, we were able to demonstrate for the first time InGaAs/SiGe CMOS circuits obtained by selective epitaxy on Si substrates [3]. In particular, we demonstrated that 6T-SRAM cells can be fabricated with cell sizes down to 0.4 μm2, which is a major milestone towards the large-scale manufacturing of this technology.

This technology can be extended to many other applications than CMOS. Indeed, thin virtual substrates of InP can be integrated on Si in this way and subsequently used to integrate RF or photonics heterostructures.

3d integration

Etching the SiGe-on-insulator wafer (a) defines the pFET active region and (b) an opening for the silicon seed.
(c) Sacrificial material is then added before capping with an oxide and adding an opening to this layer.
(d) Sacrificial material is removed before InGaAs grows from (e) the seed through (f) the neck to fill (g) the cavity.
(h) The oxide cap is removed before forming (i) an nFET active region and ultimately InGaAs nFETs and SiGe pFETs.
(i’) A simplified process using a common high-κ / metal gate has been demonstrated.


Growth dynamics

A good understanding of the epitaxy process is essential for enabling high-performance materials and devices as well as for developing strategies for cointegration.

We have previously studied the growth of “bottom-up” III–V nanowires using selective area growth (SAG) in oxide mask openings [4]. Whereas this SAG yields NWs free from detrimental structural defects, attainable NW geometries, surface and growth orientation are very limited because of surface diffusion and reaction kinetics of the precursor molecules and nanowire-free surface energies. This has inspired us to develop an alternative method based on epitaxy in templates that can alleviate many of the above constraints. We started with the initial demonstration of III–V heterostructures on Si (111) in a SiO2 template and have progressed to much more complex structures, devices and integration schemes. For a recent review [5].

We found that the crystal growth in the template follows classical crystal growth physics. After initial nucleation, favorable growth planes develop and, depending on the growth conditions, prevail throughout the filling process.

The material delivery from the gas phase mixture into the template differs from classical selective-area growth or bottom-up nanowire growth processes because of the long surface diffusion path on the template and very small exposed III–V surface [6].

Growth dynamics

Illustration of molecular transport into a template (left). Schematic and corresponding SEM images of InAs crystal facet formation during MOCVD.


Bonding

monolithic bondingDirect wafer bonding is used to transfer thin layers of III–V onto silicon substrates as the industry is currently doing to build silicon-on-insulator (SOI) substrates. The required InGaAs layer is grown on a donor substrate, which is then bonded via an oxide to a target silicon substrate. The thin III–V layer is then released from the donor wafer, yielding a III–V-on-insulator structure on Si [7].

The donor wafer can be recycled in order to maintain the cost efficiency of this process [8]. Having a very thin III–V channel on an insulator is the ideal structure to maintain good electrostatic control of the gate over the channel at short gate lengths. It also efficiently cuts leakage currents from source to drain. In addition, it enables the use of the back-biasing technique, which permits the transistor operation to be adjusted dynamically to make it either faster or more power-efficient. All these arguments are strong reasons why III–V-on-insulator structures might be the preferred option when addressing mobile applications.

monolithic bonding We have mastered this technique and demonstrated that it can be scaled to large-size III–V-on-insulator on Si substrates. By using an epitaxial III–V on Si donor wafer [9,10], we can apply it to pre-processed CMOS wafers in order to stack several layers of active components in a 3D monolithic fashion [11,12]. We have used this technique for the first-of-a-kind demonstration of an InGaAs/SiGe CMOS technology on Si [13].

Furthermore, we have extended this technique to many other III–V materials beyond InGaAs as well as other non-III–V materials such as crystalline oxides. Among other things, we can use this technique to integrate InAs or GaSb on Si for further development of low-power logic circuits, GaP on Si for quantum opto-mechanics applications, or even barium–titanate on SOI for photonics applications.


Publications

[1] L. Czornomaz, E. Uccelli, M. Sousa, V. Deshpande, V. Djara, D. Caimi, M. Rossell, R. Erni, J. Fompeyrine,
Confined Epitaxial Lateral Overgrowth (CELO): A Novel Concept for Scalable Integration of CMOS-compatible InGaAs-on-insulator MOSFETs on Large-Area Si Substrates,”
Symposium on VLSI Technology, pp. T172–T173, Aug. 2015.

[2] H. Schmid, M. Borg, K. Moselund, L. Gignac, C.M. Breslin, J. Bruley, D. Cutaia, H. Riel
Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si,”
Appl. Phys. Lett. 106, 233101 (2015).

[3] L. Czornomaz, V. Djara, V. Deshpande, E. O’Connor, M. Sousa, D. Caimi, K. Cheng, J.Fompeyrine,
First Integration of InGaAs/SiGe Channels into Dense SRAM Arrays with sub-0.45 m2 Cell Size Fabricated Using Standard CMOS Processes,”
Symposium on VLSI Technology, p. T9-2, June 2016.

[4] M.T. Björk, H. Schmid, C.M. Breslin, L. Gignac, Heike Riel,
InAs nanowire growth on oxide-masked 〈111〉 silicon,”
Journal of Crystal Growth 344(1) 31-37, 2012.

[5] F. Menges, F. Motzfeld, H. Schmid, P. Mensch, M. Dittberner, S. Karg, H. Riel and B. Gotsmann,
Local Thermometry of Self-heated Nanoscale Devices (Invited),”
IEEE International Electron Devices Meeting (IEDM) 2016.

[6] M. Borg, H. Schmid, K.E. Moselund, D. Cutaia, H. Riel,
Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si,”
J. Appl. Phys. 117(14) 144303, 2015.

[7] L. Czornomaz, N. Daix, P. Kerber, K. Lister, D. Caimi, C. Rossel, M. Sousa, E. Uccelli, J. Fompeyrine,
Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon,”
Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp. 143–146, Sept 2013.

[8] L. Czornomaz, N. Daix, D. Caimi, M. Sousa, R. Erni, M. Rossell, M. El-Kazzi, C. Rossel, C. Marchiori, E. Uccelli, M. Richter, H. Siegwart, J. Fompeyrine,
An integration path for gate-first UTB III–V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling,”
IEEE International Electron Devices Meeting (IEDM), 23.4.1, 2012.

[9] N. Daix, E. Uccelli, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, J. M. Hartmann, K.-T. Shiu, C.-W. Cheng, M. Krishnan, M. Lofaro, M. Kobayashi, D. Sadana, J. Fompeyrine,
Towards large size substrates for III-V co-integration made by direct wafer bonding on Si,”
Applied Physics Letters – Materials 2(8), 086104, 2014.

[10] V. Djara, V. Deshpande, E. Uccelli, N. Daix, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, J. Hartmann, K.-T. Shiu, C.-W. Weng, M. Krishnan, M. Lofaro, R. Steiner, D. Sadana, D. Lubyshev, A. Liu, L. Czornomaz, J. Fompeyrine,
An InGaAs on Si platform for CMOS with 200 mm InGaAs–OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch,”
Symposium on VLSI Technology, pp. T176–T177, June 2015.

[11] V. Deshpande, V. Djara, E. O’Connor, P. Hashemi, K. Balakrishnan, M. Sousa, D. Caimi, A. Olziersky, L. Czornomaz, J. Fompeyrine,
Advanced 3D Monolithic Hybrid CMOS with Sub-50 nm Gate Inverters Featuring Replacement Metal Gate (RMG)–InGaAs nFETs on SiGe–OI Fin pFETs,”
IEEE International Electron Devices Meeting (IEDM), pp. 8.8.1–8.8.4, Dec. 2015.

[12] V. Deshpande, V. Djara, E. O’Connor, P. Hashemi, K. Balakrishnan, D. Caimi, M. Sousa, L. Czornomaz, J. Fompeyrine,
DC and RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe–OI FinFETs fabricated by 3D monolithic integration,”
Solid State Electronics 128, pp. 87-91, Feb. 2017.

[13] L. Czornomaz, N. Daix, K. Cheng, D. Caimi, C. Rossel, K. Lister, M. Sousa, J. Fompeyrine,
Co-integration of InGaAs n-and SiGe p-MOSFETs into digital CMOS circuits using hybrid dual-channel ETXOI substrates,”
IEEE International Electron Devices Meeting (IEDM), pp. 2.8.1–2.8.4, Dec 2013.