III–V on silicon photonics

Silicon photonics is a versatile photonic integration platform that leverages the infrastructure and fabrication processes known from standard CMOS technology.

Consequently, silicon photonics structures can be fabricated in CMOS foundries at low cost, as known from microelectronics. Silicon’s transparency for wavelengths greater than 1.1 µm makes this technology very attractive for a wide range of applications in the datacom and telecom industries, which operate in the wavelength windows around 1.3 and 1.55 µm, respectively.

The main application is in silicon photonics-based transmitters and receivers for optical interconnects, but there is great potential for broadening the scope to such applications as sensing.

Silicon photonics wafer

A. Silicon photonics wafer after planarization.
Bonded III–V epitaxial material on top of silicon photonic wafer.
C. Optical and scanning electron microscope images of fabricated device (photodetector).

Today, silicon photonic chips, as fabricated in CMOS foundries, combine various building blocks such as passive waveguides to distribute the light on the chip, wavelength filters, phase and intensity modulators and photodetectors. It is even possible to monolithically co-integrate photonic devices with CMOS electronics on the same chip.

However, silicon is a poor light emitter due to its indirect bandgap. This requires the integration of other materials, such as those from the III–V group, e.g. indium phosphide (InP), for realizing efficient on-chip light sources.

A viable path to integrate the III–V materials on silicon photonics is bonding. For this we grown high-quality layer stacks epitaxially on InP wafers and then transfer them to silicon wafers. The layer stack consists of multiple quantum well layers that show luminescence upon electrical pumping.

By integrating the III–V material in an optical cavity, we achieve optical amplification and lasing. Laser devices with good performance have been shown on silicon using this technology. However, integrating these lasers into a fully CMOS processed chip with both standard front-end (transistors and silicon photonics) and back-end (on-chip electrical wiring) has not yet been demonstrated.

The goal of our pro­ject is to rea­lize fully CMOS-embed­ded la­sers on sil­i­con com­bined with elec­tri­cal and opt­i­cal func­tions.

—IBM scientist Kirsten Moselund

The goal of our project is to overcome this challenge and realize fully CMOS-embedded lasers on silicon combined with electrical and optical functions. That will open a completely new range of applications.

To integrate the III–V layer into the CMOS process flow, the III–V material is kept very thin (<200 nm). This way, it is compatible with the thicknesses of the dielectric layers in the back-end of the line stack [1].

Integrating on-chip laser sources into the CMOS process flow offers unique advantages compared to other integration approaches.

The monolithic combination of electrical devices with passive and active optical structures extends the silicon photonics platform with a range of unique new functionalities.

The integrated light source(s) can be controlled by the electronics for such applications as direct high-speed modulation, power stabilization and wavelength tuning.

The form factor and scalability is massively improved compared to hybrid integration approaches. The power efficiency is optimized as optical coupling losses from external lasers to the silicon photonics chip are abandoned.

Furthermore, the co-processing of lasers onto the silicon wafer will lead to a massive cost reduction for two reasons. First, co-processing the laser structures on the large-sized silicon wafers is more economical. Second, this greatly reduces the hybrid laser assembly costs.

[1] J. Hofrichter et al.,A mode-engineered hybrid III-V-on-silicon photodetector,” European Conference on Optical Communication (ECOC), pp. 1-3, 2015.

Ask the experts

Bert Jan Offrein

Bert Jan Offrein

IBM Research scientist

Kirsten E. Moselund

Kirsten E. Moselund

IBM Research scientist

Projects & collaboration

This work is in collaboration with the Materials Integration and Nanoscale Devices (MIND) group at IBM Research – Zurich.

Our project receives funding from the following European Union’s FP7 and H2020 research and innovation programs:

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