Low-power electronics
Today’s electronics are increasingly power-constrained. This is the case both for high-performance computing, where our ability to move to exascale computing is limited by the power consumption of supercomputers, and for relatively low-performance applications in IoT, where we wish to increase battery lifetimes.
The increasing demand to collect and analyze large volumes of data has led to an explosion of energy consumption in data centers, which is increasing exponentially over time.
As both active and passive power consumption rates scale with supply voltage (VDD), reducing the supply voltage is the main lever to decrease passive and dynamic power consumption. Voltage scaling in advanced technology nodes has not been able to keep up with dimensional scaling, and the scaling of operating voltages beyond 0.5 V poses a problem to MOSFETs.
“In 2050, the energy consumption of data centers worldwide is predicted to amount to three times the electric power generated in Japan by 2010.”
—Compiled by TDK, based on the GPC Survey and estimation committee report 2008.
The inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of
where kB is Boltzmann’s constant, T is the temperature, q the elementary charge, Cd the depletion layer capacitance and Cox the gate-oxide capacitance. At 300 K, this results in an ideal value of 59.5 mV/dec, which is usually referred to as the 60 mV/dec limit of the MOSFET. Hence, there is a fundamental limit of how steep the turn-on of the MOSFET can be, independent of device design or charge carrier mobility in the material.
At higher bias levels, tunneling is less efficient than current mechanisms compared to drift diffusion in a MOSFET, but at voltage levels below 0.5 V it is hoped that tunnel FET might provide steep subthreshold swing combined with a higher current than in a comparable MOSFET.
Tunnel FETs
Tunnel FETs are based on the quantum-mechanical operating mechanisms of band-to-band tunneling (BTBT). The energy-filtering mechanism provided by BTBT allows us to achieve SS below 60 mV/dec and to reduce VDD and therefore the overall power consumption. Subthermal minimum slopes have been demonstrated, as have devices with high Ion. Great progress has been achieved in recent years. However, experimentally observed slopes averaged over 2–3 decades of current combined with current levels comparable to that of a MOSFET are still greater than 60 mV/dec.
The key point in a TFET is the possibility to control the device on–off switch by properly biasing a gated p–i–n structure, where the intrinsic region is the transistor channel and the doped regions are the source and the drain. When source conduction band and channel valence band are not aligned, ideally no BTBT occurs and the device is in the off state (except for extremely low subthreshold currents). As soon as a gate bias is applied, the bands in the channel are pulled up and only the carriers within a certain energy window in the source can tunnel towards available energy states into the channel valence band.
Silicon-based TFETs are good for achieving low SS, but the fairly large bandgap of silicon means that they can provide only low on-current levels. With low bandgap materials such as InAs, one may achieve high Ion, but the Ion/Ioff ratio is reduced.
III–V heterostructures can provide a perfect tradeoff for this purpose because they can a combine small effective tunneling mass and narrow staggered or broken band heterojunction alignment, leading potentially to both high Ion and low SS. Moreover, unlike silicon, most of the III–V compound semiconductors have a direct bandgap, which also enhances tunneling efficiency.
“At IBM, our focus is on technologies that may be integrated on and with Si CMOS.”
—IBM scientist Kirsten Moselund
Our focus
At IBM, our focus is not only on making a single good device, but on technologies that may be integrated on and with Si CMOS, as this is essential if tunnel FETs will make it to the VLSI integration level. Initially we focused on the p-channel device, based on a vertical nanowire Si channel to provide a gate stack with a low defect density, combined with an InAs heterojunction source.
Throughout the years, we have achieved a number of device innovations, such as going from selective epitaxy to TASE growth, replacing organic isolation layers with inorganic ones and introducing metal ALD as the gate stack.
We have also demonstrated the importance of an optimum gate control by scaling EOT and the vertical nanowire dimension, which leads to improvements in both Ion and subthreshold swing.
On all our TFET work we collaborate very closely with the simulation group of Prof. Andreas Schenk at ETHZ to gain a deeper understanding of device physics and functionality. In particular, we have studied extensively the impact of various trap-related phenomena and their impact on device performance.
Complementary TFET technologies are complicated by the requirement for different heterojunctions for the p- and n-channel devices. Recently we reported for the first time p-type InAs–Si and n-type InAs–GaSb heterostructure TFETs in-plane on a silicon-on-insulator (SOI) substrate. This was both the first demonstration of any in-plane heterojunction TFETs on a silicon platform, as well as the only scalable approach for complementary heterojunction tunnel FET technology.
Transfer characteristic of in-plane InAs–Si TFET at 300 and 125 K. Symbols represent experimental data points, whereas lines represent simulations carried out by the group of Prof. Andreas Schenk at ETHZ.
Schematic of p and n-TFETs fabricated in compatible process flows, but currently on separate wafers for ease of fabrication.
Top view of false-colored SEM images of p-TFET and n-TFET with insets showing device cross sections in the individual materials regions.
Tunnel diodes
Insight into device physics
In parallel to our TFET work, we continue to explore tunnel diodes in different materials systems. The tunnel diodes are not complicated by the presence of the gate stack, and hence provide an easier means to separate the physical effects related to the junction itself. This is the reason we are working in parallel on the two-terminal counterpart of TFETs: achieving a good understanding of channel band alignment, junction abruptness, tunnel-barrier transparency and interface defects is crucial to improving TFET performance.
InAs–Si and InAs–GaSb tunnel diodes have been fabricated and characterized, which provides statistical data about channel diameter and doping profile dependence. DC IV combined with low-temperature measurements provide means for investigating band alignment, whereas more sophisticated tunneling spectroscopy can be used to gain insights into the nature and distribution of defect states.
Tunneling spectroscopy applied to an InAs–Si Esaki diode to investigate trap-assisted tunneling at the heterojunction.
Ask the experts
Collaboration
Prof. Adrian Ionescu
EPF Lausanne
Prof. Andreas Schenk
ETH Zurich
E2 SWITCH and STARnet Center for Low Energy System Technology (LEAST)
IBM has been co-organizing annual international workshops on steep slope devices
- 2017 UC Berkeley, USA
- 2016 EPFL Lausanne, Switzerland
- 2015 University of Notre Dame, USA
Related EU projects
E2 Switch
Energy Efficient Tunnel FET Switches and Circuits
STEEPER
Steep subthreshold slope switches for energy efficient electronics
Guardian Angels
Flagship pilot for zero-power systems
Publications
[1] “III-V Heterostructure Tunnel Field-Effect Transistor”
C. Convertino et al.
Accepted, Journal of Physics: Condensed Matter, 2018.
[2] “Investigation of InAs / GaSb tunnel diodes on SOI”
C. Convertino et al.
In Proc. EUROSOI-ULIS 2017, pp. 148–151, 2017.
[3] “Complementary III-V Heterojunction Tunnel FETs Monolithically Integrated on Silicon”
C. Convertino et al.
ECS Meeting Abstracts, 2017.
[4] “The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs”
A. Schenk et al.
In Proc. Simulation of Semiconductor Processes and Devices (SISPAD), 2017.
[5] “The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si tunnel FETs”
A. Schenk et al.
In Proc. 17th International Workshop on Junction Technology (IWJT), 27-30, 2017.
[6] “Lateral InAs/Si p-type tunnel FETs integrated on Si—Part 2: Simulation study of the impact of interface traps”
S. Sant et al.
IEEE Transactions on Electron Devices 63(11) 4240-4247, 2016.
[7] “Lateral InAs/Si p-type tunnel FETs integrated on Si. Part 1: Experimental devices. Part 2: Simulations”
K.E. Moselund et al.
IEEE Trans. Electron Devices 63(11) 4233–4239, 2016.
[8] “Complementary III-V heterojunction lateral NW tunnel FET technology on Si”
D. Cutaia et al.
In Proc. VLSI Symposium on Technology, 2016.
[9] “Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates”
D. Cutaia et al.
IEEE Journal of the Electron Devices Society 3(3), 176-183, 2015.
[10] “Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs”
D. Cutaia et al.
(Best student paper) In Proc. EUROSOI-ULIS Conference, pp. 61-64, 2015.
[11] “Tunneling and occupancy probabilities: How do they affect tunnel-FET behavior?”
L. De Michielis et al.
IEEE Electron Device Letters 34(6), 726-728, 2013.
[12] “InAs–Si nanowire heterojunction tunnel FETs”
K.E. Moselund et al.
IEEE Electron Device Letters 33(10), 1453-1455, 2012.
[13] “Silicon nanowire Esaki diodes”
H. Schmid et al.
Nanoletters 12, 699. 2012.
[14] “InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs”
H. Riel et al.
In Proc. International Electron Devices Meeting (IEDM), 16.6, 2012.
[15] “Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors”
H. Schmid et al.
In Proc. Device Research Conference (DRC), pp.181-182, 2011.
[16] “Silicon nanowire tunnel FETs: low-temperature operation and influence of high-gate dielectric”
K.E. Moselund et al.
IEEE Transactions on Electron Devices 58(9), 2911-2916, 2011.
[17] “Tunnel field-effect transistors as energy-efficient electronic switches”
M. Ionescu, H. Riel
Nature 479 (7373), 329-337, 2011.
[18] “Si–InAs heterojunction Esaki tunnel diodes with high current densities”
M.T. Björk et al.
Applied Physics Letters 97, 163501, 2010.
[19] “Comparison of VLS grown Si NW tunnel FETs with different gate stacks”
K.E. Moselund et al.
In Proc. European Solid State Device Research Conference, 2009.
[20] “Silicon nanowire tunneling field-effect transistors”
M.T. Björk et al.
Applied Physics Letters 92(19), 3504, 2008.
[21] “VLS-grown silicon nanowire tunnel FET”
K.E. Moselund et al.
In Proc. Device Research Conference, 23-24, 2009.