Today’s electronics are increasingly power-constrained. This is the case both for high-performance computing, where our ability to move to exascale computing is limited by the power consumption of supercomputers, and for relatively low-performance applications in IoT, where we wish to increase battery lifetimes.
The increasing demand to collect and analyze large volumes of data has led to an explosion of energy consumption in data centers, which is increasing exponentially over time.
As both active and passive power consumption rates scale with supply voltage (VDD), reducing the supply voltage is the main lever to decrease passive and dynamic power consumption. Voltage scaling in advanced technology nodes has not been able to keep up with dimensional scaling, and the scaling of operating voltages beyond 0.5 V poses a problem to MOSFETs.
“In 2050, the energy consumption of data centers worldwide is predicted to amount to three times the electric power generated in Japan by 2010.”
The inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of
where kB is Boltzmann’s constant, T is the temperature, q the elementary charge, Cd the depletion layer capacitance and Cox the gate-oxide capacitance. At 300 K, this results in an ideal value of 59.5 mV/dec, which is usually referred to as the 60 mV/dec limit of the MOSFET. Hence, there is a fundamental limit of how steep the turn-on of the MOSFET can be, independent of device design or charge carrier mobility in the material.
At higher bias levels, tunneling is less efficient than current mechanisms compared to drift diffusion in a MOSFET, but at voltage levels below 0.5 V it is hoped that tunnel FET might provide steep subthreshold swing combined with a higher current than in a comparable MOSFET.
Schematic of p and n-TFETs fabricated in compatible process flows, but currently on separate wafers for ease of fabrication.
Top view of false-colored SEM images of p-TFET and n-TFET with insets showing device cross sections in the individual materials regions.