Adiabatic optical coupling

Integrated CMOS-based silicon (Si) photonics monolithically combines electrical and optical functions on a single Si chip. Silicon photonics is regarded as the top candidate to provide bandwidth scalability by the fundamental scale-out properties of integrated technology and by introducing additional functions such as wavelength division multiplexing (WDM) or higher-order modulation formats. All necessary Si-photonics building blocks have been already demonstrated [1].

To enable cost-effective and scalable system-level integration of Si-photonics transceiver chip, we establish a radically new approach in which a Si-photonics chip is co-packaged with the data-processor chip directly on a carrier substrate (Fig. 1).

System-level integration schemes of Si-photonics chip co-packaged on a processor package.

Figure 1. System-level integration schemes of Si-photonics chip co-packaged on a processor package.

Such tight electro-optical integration can provide off-carrier bandwidth in excess of 10 Tb/s. This is obtained by increasing the number of physical optical channels and exploiting the WDM capabilities offered by Si photonics.

The Si-photonics chip is now co-packaged with the ASIC CPU or switch chip. This allows a smaller footprint and hence results in a higher bandwidth density. Improved electrical signaling is also obtained because of the short electrical interconnects with fewer interfaces between the electro-optical transceiver and the data processing elements.

As our objective is to realize scalable system-level integration, as depicted in Fig. 1a, a new optical interface approach needs to be provided. We target an optical coupling scheme that can enable broadband and efficient coupling between a large number of on-chip Si waveguides and the external world.

Single-mode (SM) polymer waveguides (PWGs) are used to distribute the optical signals between the various subsystems across the optical printed circuit board (PCB) and to establish the interface between the Si-photonics chip and the fiber cables.

Figure 1(b) shows a scheme of the envisioned system-level package approach.

The large optical modal mismatch between the on-chip Si waveguide (typically measuring a few hundred nanometers in height and width) and a larger SM PWG mode-matched with a standard SM fiber (approx. 10 µm), can be solved by realizing an adiabatic transformation of the optical mode of a Si-waveguide to the mode of the SM PWG. This is accomplished by inverse tapering the Si-waveguide end and bringing it in very close proximity or in direct physical contact with the PWG.

Figure 2 shows a scheme where a Si-photonics chip is attached to a carrier with PWGs. The optical power of the guided mode in the Si waveguide is transferred to the mode of the SM PWG because the Si-waveguide width is slowly tapered to reduce its effective index.

This method is fully compatible with established electrical assembly techniques (e.g., solder-reflow, flip-chip bonding). It allows simultaneous electro-optical interfacing and is scalable to many optical channels.

System-level integration schemes of Si-photonics chip co-packaged on a processor package.

Figure 2. (a) Schematic of the Si-photonics chip assembly to the carrier with SM PWG processed. (b) Close-up of the Si-to-PWG core configuration scheme for the adiabatic optical power transfer.

Recent works were published targeting specifically a Si-waveguide-to-PWG system with multiple optical I/Os. We reported on the design, fabrication, and experimental proof of concept of adiabatic optical coupling between an array of Si-waveguides in a Si-photonics chip and an array of SM PWGs.

The Si-photonics chip was flip-chip bonded onto SM PWGs processed on a separate substrate, as shown in Fig. 3.

Flip-chip bonded Si-photonics chip

Figure 3. (a) Flip-chip bonded Si-photonics chip on a separate chip containing PWG scheme and (b) sample.

Optical coupling losses ≤1 dB for adiabatic optical couplers with taper lengths ≥1.0 mm were measured. Low-loss optical coupling was verified experimentally in the spectral window of the O-band (around 1310 nm) and C-band (around 1550 nm) for both TE and TM polarized light.

Furthermore, this optical coupling scheme is tolerant against lateral misalignment of the Si chip with respect to the polymer waveguide structures. A misalignment of ±2 μm led to a loss increase of only less than 1 dB. Negligible optical back reflections (<50 dB) were found from the adiabatic coupler [2–5].


 [1] S. Assefa et al.,A 90nm CMOS integrated nano-photonics technology for 25Gbps WDM optical communications applications,” IEEE Electron Devices Meeting (IEDM), pp. 33.8.1–33.8.3, 2012

[2] I. M. Soganci et al.,Flip-chip optical couplers with scalable I/O count for silicon photonics,” Optics Express 21(13) 16075–16085, 2013.

[3] A. La Porta et al.,Silicon photonics packaging for highly scalable optical interconnects,” IEEE 65th Electronic Components and Technology Conference (ECTC), pp. 1299–1304, 2015.

[4] A. La Porta et al.,Optical Coupling between Polymer Waveguides and a Silicon Photonics Chip in the O-band,” in Optical Fiber Communication Conference, OSA Technical Digest (online) paper M2I.2, 2016.

[5] A. La Porta et al.,Scalable Optical Coupling between Silicon Photonics Waveguides and Polymer Waveguides,” IEEE 66th Electronic Components and Technology Conference (ECTC), pp. 461-467, 2016.

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Bert Jan Offrein

Bert Jan Offrein

IBM Research scientist

Group members

Roger Dangel
Folkert Horst
Daniel Jubin
Antonio La Porta
Norbert Meier

Projects & collaboration

The work is partially funded by EU projects

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