Enterprise solid-state storage

 

In order to evaluate new algorithms and techniques for iterative MLC programming and cell-state sensing, it is necessary to implement them in circuitry.

We are engaged in analog and digital design in addition to bring-up and testing of advanced circuitry for novel sensing and programming schemes for multilevel-cell phase change memory. Our designs serve both as small proof-of-concept evaluation vehicles, as well as larger development vehicles [2011-3, 2011-6, 2013-3].

In the past, we have designed and implemented circuitry for multilayer cell iterative programming, as well as electrical resistance readout on phase change memory cells.

A 256-Mcell, 2-bit/cell MLC phase change memory chip has been fabricated on 90-nm technology, in collaboration with the IBM Burlington fabrication team and the T.J. Watson Research Center (Fig. 1).

The circuit design has several main objectives. On the one hand, it aims to develop circuitry that optimizes the silicon implementation area, and on the other, it aims to minimize processing latency, while offering good noise immunity [2010-3]. Typically, these are conflicting requirements that pose several tradeoffs.

Our objective in circuit design research is to achieve the best possible tradeoff regarding the implementation of advanced read and write algorithms in silicon.

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Illustration of a 256 Mcell MLC PCM chip with 2 bits/cell storage.ategy for the detection of stored levels in MLC PCM. onventional low-field resistance metric

Figure 1. Illustration of a 256 Mcell MLC PCM chip with 2 bits/cell storage.