Computational scaling

Project overview

It is widely expected that lithography for the 22 nm CMOS chip fabrication process will still need to use a 193 nm light source. This puts tremendous pressure on the design process and the mask technology that need to overcome the two-dimensional bandwidth limitations of the lithographic process. The required amount and complexity of processing will be very large, which explains the term “computational scaling” (CS). Source / mask optimization (SMO) and optimized design rules are two of the main techniques IBM is pursuing for its computational scaling solution [1].

Our team in ZRL is developing novel 2D pattern recognition and analysis techniques to address these two requirements for CT design methodology. In a first activity, we are designing a clustering technique and a methodology to select the critical patterns from a chip layout design, which will be used to optimize the exposure process. We are improving feature extraction, clustering techniques and pattern selection algorithms, as well as optimizing the pattern window size. In our second activity we are developing techniques to remove data redundancy to accelerate optical design rule checking. We are designing a learning classifier and optimizing training and production operations.


  1. IBM Develops Computational Scaling Solution for Next Generation "22nm" Semiconductors, press release, 17 Sep 2008.