Journals
T. Knobloch et al. “Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning,” Nature Electronics, 2022
M. Imani et al. “Metasurface-Programmable Wireless Network-on-Chip,” Advanced Science, 2021
A. Ganguly et al. “Interconnects for DNA, Quantum, In-Memory and Optical Computing: Insights from a Panel Discussion,” IEEE Micro, 2022
F. Lemic et al. “Survey on Terahertz Nanocommunication and Networking: A Top-Down Perspective,” IEEE Journal on Selected Areas in Communications, 36(9), 1506-1543, 2021
K. Rouhi et al. “Multi-Channel Near-Field Terahertz Communications Using Reprogrammable Graphene-Based Digital Metasurface,” IEEE/OSA Journal of Lightwave Technology, 2021
Y. M. Qureshi et al. “Gem5-X: A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization,” ACM Transactions on Architecture and Code Optimization (TACO), 2021
F. Ponzina et al. “E2CNN: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices,” IEEE Transactions on Computers, 2021
C.-Y. Fan et al. “Fully Integrated 2.4-GHz Flexible Rectifier Using Chemical-Vapor-Deposition Graphene MMIC Process,” IEEE Transactions on Electron Devices, 68 (1326), 2021
M. Saeed et al. “Voltage-Tunable Thin Film Graphene-diode-based Microwave Harmonic Generator,” IEEE Microwave and Wireless Components Letters, 2021
Z. Wang et al. “Graphene in 2D/3D Heterostructure Diodes for High Performance Electronics and Optoelectronics ,” Adv. Electron. Mat., 2021
F. Glaser et al. “Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters,” IEEE Transactions on Parallel and Distributed Systems, 32(3), 633-648, 2021
A. Garofalo et al. “XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes ,” IEEE Transactions on Emerging Topics in Computing, 2021
A. Burrello et al. “DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs,” IEEE Transactions on Computers, 2021
S. Abadal et al., “Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors,” arXiv preprint, arXiv:2011.04107, 2020
L. Duch et al., “Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 2122 - 2133, 2020.
A. Elnaqib et al., “A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2020.
W.A. Simon et al., “An in-Cache Computing Architecture for Edge Devices,” IEEE Transactions on Computers, 2020.
A. Levisse et al., “Write Termination circuits for RRAM: An Holistic Approach From Technology to Application Considerations,” IEEE Access 8, 109297–109308, 2020.
X. Timoneda et al., “Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication,” IEEE Transactions on Communications 68(5), 3247–3258, 2020.
S. Abadal et al., “Wave Propagation and Channel Modeling in Chip-Scale Wireless Communications: A Survey from Millimeter-Wave to Terahertz and Optics,” IEEE Access 8, 278–293, 2019.
Conference Publications
R. Guirado et al., “Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing,” in Pro. IJCNN/WCCI 2022, Padova, Italy, July 2022.
N. Bruschi et al., “Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference,” in Proc. AICAS 2022, Incheon, Korea, June 2022
R. Guirado et al., “Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package,” in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, January 2021.
M. A. Rios et al., “Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing,” in Proc. Design, Automation and Test in Europe Conference (DATE), Virtual Conference and Exhibition, February 1-5, 2021
G. Ottavi et al., “End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?” in Proc. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021.
J. Klein et al., “Architecting More Than Moore - Wireless Plasticity for Massive Heterogeneous Computer Architectures (WiPLASH)” in Proc. ACM International Conference on Computing Frontiers (CF), 2021.
A. Franques et al., “WiDir: A Wireless-Enabled Directory Cache Coherence Protocol,” in Proc. HPCA-27, Seoul, South Korea, February 2021.
A. Franques et al., “Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Many-Core CMPs,” in Proc. DATE 2021, Grenoble, France, February 2021.
W. A. Simon et al., “A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance,” in Proc. IFIP/IEEE International Conference on Very Large Scale Integration, 2020.
M. Imani et al., “Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface,” ACM International Workshop on Nanoscale Computing, Communication, and Applications (NanoCoCoA), virtual, November 2020.
H. Okuhara et al., “An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain, pp. 1-5, 2020.
G. Ottavi et al., “Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, pp. 512-517, 2020.
W. A. Simon et al., “A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance,” in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Salt Lake City, Utah, USA, 2020.
N. Bruschi et al., “Enabling mixed-precision quantized neural networks in extreme-edge devices,” in Proc. 17th ACM International Conference on Computing Frontiers (CF ’20). Association for Computing Machinery, New York, NY, USA, pp. 217–220, 2020.
A. Levisse et al., “Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Barcelona, Spain, 2020, pp. 1549–1552.
H. Najibi et al., “Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology,” in Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020.
H. Najibi et al., “Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoC with On-Chip Switched Capacitor Converters,” in Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020. (Best Paper Award)
R. Guirado et al., “Understanding the Impact of On-Chip Communication on DNN Accelerator Performance,” in Proc. ICECS ’19, Genova, Italy, November 2019.
Invited Talks, Lectures & Panels
S. Abadal, “Graphene-based Wireless Communications for Networks-on-Chip,” Future Internet Networks course of the Master in Innovation and Research in Informatics (MIRI), Facultat d'Informàtica de Barcelona (FIB), Universitat Politècnica de Catalunya (UPC), December 2019, 2020, and 2021.
S. Abadal,
“Towards the Internet of Everything with Graphene Antennas and Reconfigurable Intelligent Surfaces,” Keynote at the 4th International Conference on Emerging Technology Trends in Electronics, Communication and Networking, Surat, India, November 2021.
Video
S. Abadal,
“Graphene nano-antennas for wireless communications at the chip scale,” at the 3rd Annual Congress of Nanoscience and Nanotechnology, Barcelona, Spain, November 2021.
Video
S. Abadal and A. Jain, “Towards the internet of everything: THz wireless networks for next generation compute platforms,” in the WWRF Workshop of THz Waves: Fast Lane Journey to 6G, Wireless World Research Forum, Virtual Event, April 2021.
S. Abadal, “Towards Wireless-enabled Multicore Computer Architectures,” University of Glasgow, March 2021.
S. Abadal, “Wireless Communications in the Terahertz Band for Massive Heterogeneous Computer Architectures,” 3rd Towards TeraHertz Communications workshop, Virtual Event, March 2021.
S. Abadal and I. Boybat, “Wireless communications at the chip scale for future multi-chip processors,” Women's Week UPC, Universitat Politècnica de Catalunya, Spain, March 2021.
D. Rossi, “Extending RISC V Platforms for ML at the Extreme Edge of the IoT” ISSCC FORUM, Feb. 2021.
S. Abadal, “Wireless Plasticity for Massive Heterogeneous Computer Architectures,” Heterogeneity Alliance workshop, HiPEAC 2021, Budapest, Hungary, Jan. 2021.
S. Abadal and M. Zapater, “Nanocomunicacions: Creant xarxes WiFi de la mida del vostre polze,” Institut El Pi Gros, Sant Cebrià de Vallalta, Spain, Jan. 2021.
Z. Wang, “Wafer Scale Integration of Graphene – Progress and Outlook,” Graphene 2020 Online Conference, Oct. 2020.
Z. Wang, “Metal-Insulator-Graphene RF Diodes: From Devices to Integrated Circuits,” Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) devices with IEEE EDS Mini-Colloquium on „Non-conventional Devices and Technologies“, October 2020.
A. Sebastian et al., “Unconventional computing and what it means for the future of interconnects,” International Workshop on Network on Chip Architectures (NoCArc), held within the IEEE/ACM International Symposium on Microarchitecture, October 2020.
S. Abadal and F. Lemic, “Terahertz Nanocommunication and Networking: Emerging Applications, Approaches, and Open Challenges,” ACM International Conference on Nanoscale Computing and Communication (NANOCOM), September 2020.
A. Levisse et al., “Demonstrating In-Cache Computing Thanks to Cross-Layer Design Methodologies,” Design Automation and Test in Europe (DATE), Special Session on In-Memory Computing for Edge AI, Grenoble (FR), Virtual Event April 2020.
A. Levisse et al., “Rendre efficace l’intelligence artificielle dans l’Edge grâce aux technologies et architectures mémoires émergentes,” Francophone winter school on design techniques for embedded systems design (Ecole d’Hiver francophone sur la technologie de conception des systèmes embarqués hétérogènes – FETCH), Montréal, Canada, Feb. 2020.
Workshops & Tutorials
M. Zapater et al., Tutorial: “Using gem5 and full- system RISC-V simulation to enable the optimization of heterogeneous architectures,” High Performance and Embedded Architecture and Compilation (HiPEAC), January 2021.
This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 863337.
Project Coordination: Sergi Abadal (UPC)
www.upc.edu