Charge Noise in Semiconductor Spin Qubits

Scope

With this WE Heraeus Fast Track Symposium on charge noise in spin qubits we would like to bring together experts from Europe and overseas to discuss the origins and impact of charge noise in spin qubit devices. We believe that this timely topic requires a very focused technical meeting with a small group of participants that have a strong technical background on this topic. We will exchange ideas and findings regarding quantitative comparisons of charge noise in different spin qubit platforms, mitigation strategies (improved materials and fabrication, surface treatments, filtering) and operation at sweet spots which reduces the noise sensitivity while preserving operation speed. To compare a large range of silicon and germanium-based platforms (holes and electrons, MOS, Ge and Si quantum wells and GeSi nanowires) we include in our discussion also questions related to nuclear spin noise and valley splitting which are not directly linked to charge noise but give rise to related trade-offs.

The goal of the symposium is to come up with standard characterization methods and a joint understanding of the impact of materials and fabrication processes on charge noise, and assess the strategies to resolve these issues.

Motivation

Charge noise is one of the key limitations in scaling up quantum-dot-based qubits to large scale quantum systems. While the spin state of electrons and holes is largely isolated from its charge degree of freedom, the manipulation of spin qubits with gate voltages requires some form of spin-to-charge coupling. For single-qubit gates, this coupling can be either mediated through a built-in spin-orbit interaction or by nanoscale magnetic field gradients. However, the coupling of the spin to the charge degrees of freedom makes the qubit more sensitive to uncontrolled charge or electric field fluctuations in the substrate materials, at interfaces and from electrical noise on the gates. Moreover, all known schemes for two-qubit gates entail a sensitivity to charge noise through either a tunable wavefunction overlap (exchange interaction) or a capacitive coupling, since direct magnetic spin-spin interactions are weak.

Many of the other qubit technologies (superconducting qubits, ion traps, etc.) have a comparatively large qubit footprint and have been engineered to be less susceptible to charge noise. This facilitated impressive progress to systems of 10s - 100s of qubits. In contrast to this, semiconductor spin qubits can be as small as classical transistors and therefore have great potential for scalability. However, the proximity of surfaces, interfaces and amorphous oxides and the nature of the electrically induced quantum confinement makes charge noise the key limiting factor for this platform. There is no clear consensus in the field, on how to fully characterize or mitigate this issue and many groups have their individual recipes or insights that they argue help reduce charge noise for them. In order for the field of spin qubits to progress more quickly, it is critical to discuss this challenge and to agree on standard methods for characterizing charge noise, on ways to mitigate its impact, and to compare its influence on the various spin qubit platforms.