Vision and Goals
The WiPLASH project aims to take a radical step further in computing by designing a new breed of massive heterogeneous architectures with accelerator-like performance, but without loss of purpose generality. Towards this end, WiPLASH will pioneer an on-chip wireless communication based on graphene terahertz nano-antennas able to provide architectural plasticity, reconfigurability and adaptation to the application requirements. See our position paper for more details.
To this end, the project aims to achieve three specific objectives:
- Prototype a miniaturized and tunable graphene antenna in the terahertz band
- Co-integrate graphene RF components with submillimeter-wave transceivers
- Demonstrate low-power reconfigurable wireless chip-scale networks
Project Structure
The WiPLASH research project takes a vertical approach and touches upon different aspects of design from the implementation and integration of graphene antennas to the development of heterogeneous architectures based on wireless communications within package. Research is divided into seven work packages, five of which are technical work packages. We detail them below:
- WP1: RF Design and Implementation
WP1 develops the RF, mm-wave and THz device components necessary to experimentally assess the intra-chip and inter-chip wireless communication channels within a computing package. Design and fabrication of components within the 60-300 GHz range are planned, and support for the test of graphene-enabled heterogeneous and tunable solutions may be provided. - WP2: Technological Integration
WP2 will be devoted to performing graphene integration on wafer scale with high performance required for the targeted application. Through this process, we aim to demonstrate that the graphene antenna and other graphene-based components (including diodes or larger RF components) can be co-integrated with silicon components forming the transceiver. - WP3: Wireless Communications within Package
WP3 develops mechanisms for mmWave-THz wireless communications within package, tightly coupled to the capabilities of graphene antennas and to the requirements of the architecture. More specifically, the aims are to characterize the mmWave-THz wireless channel within a computing package and to develop a protocol stack that leverages the tunability of graphene antennas and provides channel allocation, scheduling, and routing schemes that dynamically adapt to the architecture.
[Paper on channel characterization] [Paper on MAC protocols] - WP4: Architecture Design
WP4 develops a massively parallel heterogeneous architecture for artificial intelligence, exploiting the two key innovation technologies (i.e. THz wireless channels and in-memory computing accelerators) to target deep neural networks as well as novel brain-inspired computing paradigms. [Paper on DNN accelerator scale-out] - WP5: Multi-scale Simulation
WP5 develops a novel heterogeneous simulation framework leveraging the processors and accelerators from WP4 and wireless interface from WP1/2/3. The proposed framework will enable system-level thermal, application, architecture-aware simulations of a wide range of applications, including but not limited to machine learning. - WP6: Dissemination and Exploitation
- WP7: Management
Progress
Thus far, the scientific work packages of WiPLASH have focused on the following key actions during the first twelve months of execution:
- Establishing the system specifications and the measurement setup. The specifications were decided based on current and future transceiver capabilities, as well as communication requirements from the architectures.
- Prototyping the antenna. Experimental measurements are being performed on batches of metallic and graphene antennas. Theoretical analysis and simulations were used to anticipate the working point of the antennas depending on the graphene characteristics and antenna size, paving the way for a working antenna.
- Modeling the wireless channel within the computing package. Simulations in the range of 60-140 GHz have been performed assuming a flip-chip package, and these are currently being extended to 240 GHz and extended to other chip packages. This allows us to perform accurate link budget analysis and other communication-related tasks.
- Advancing in the development of heterogeneous architectures by enabling the integration in-memory cores into the design flows and simulation methods. This involves augmenting the full-system simulator of WiPLASH with ways to simulate these in-memory computing cores.
This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 863337.
Project Coordination: Sergi Abadal (UPC)
www.upc.edu