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High-performance thermal interfaces


Project overview

Moore's law describes how electronic components shrink and the numbers of transistors increase by a factor of 2 every 18 months. This causes an explosion of power density that becomes a huge problem for the industry and requires a concerted effort to develop methods to create chips with better energy efficiency and, at the same time, to improve thermal management.

Chips are mounted in computers with their active side facing downwards (flipped chip) onto a carrier that supplies power and signal lines. The upper side is covered with a copper cap and a cooler (figure top center and right). The gaps between the chip, the cap, and the cooler are filled with a thermal interface material (TIM, red lines top right) that allows the differential expansion of the chip and the cooler. These TIMs dominate the thermal resistance, causing approximately 50% of the overall thermal gradient: Thermal interfaces are key components when heat has to flow from a source to a sink that are made of different materials. Simply pressing surfaces on top of each other would create excessively large resistance to the heat flux.

Hierarchical nested channel (HNC) interfaces reduce the flow resistance of TIMs into and out of narrow (< 25 µm) gaps or bond lines by two orders of magnitude for Newtonian fluids. This allows the use of smaller bond lines with viscous thermal pastes. The effect is achieved using micrometer-sized channels that delineate primary posts and provide paths for evacuation of the paste during assembly (center). The improved squeezing speed and the thermal resistance are measured in a setup where a controlled load is applied between a heater and a cold plate (left).

HNCs provide the desired effect because local squeezing is addressed by short and narrow channels, whereas wider channels are responsible for long-range evacuation of the paste. In fact HNC interfaces offer a compromise regarding the conflicting requirements of densely packed posts, large flow channels, and large thermal contact area. For example, an HNC with 3 levels of hierarchy and 6 elements per hierarchy is shown (bottom right). With a channel width being 0.08× the pattern pitch, an overall post area > 90% results. HNCs also alleviate the voiding or paste pumping problem caused by the cyclic paste flow during heating and cooling cycles of the chip. Paste pumping causes an air bubble with branched fractal dimensions to replace the paste – an effect that is explained by the Hele Shaw theory. HNCs provide paths for paste flow, thus eliminating the growth of air bubbles (bottom, second from left).

In summary we use HNCs to reduce the thermal resistance of paste interfaces 5-10× to improve cooling efficiency and to improve resistance against paste voiding. With this effort we extend the lifetime of air cooling and create a better thermal contact for liquid coolers.

 References

[1] P.A.E. Schoen, B. Michel, A. Curioni, and D. Poulikakos, "Hydrogen-Bond Enhanced Thermal Energy Transport at Amphiphilic Silica-Water Interfaces," Phys. Rev. Lett. in press (2008).
[2] T. Brunschwiler, U. Kloter, R.J. Linderman, H. Rothuizen, and B. Michel, "HNC for Fast Squeezing Interfaces with Reduced Thermal Resistance," IEEE Trans. Comp. Packag. Technol. 30, 226 (2007).
[3] R. J. Linderman, T. Brunschwiler, U. Kloter, H. Toy, and B. Michel, "HNC for Reduced Particle Stacking and Low-Resistance Thermal Interfaces," 23rd IEEE SEMI-THERM, March, 18-22, San Jose, CA, USA, (2007). Including Best Paper Award.
[4] R. Linderman, T. Brunschwiler, B. Smith, and B. Michel, "High-Performance Thermal Interface Technology Overview," 13th THERMINIC, Sept. 17-19, Budapest, Hungary, (2007).
[5] B. Smith, T. Brunschwiler, and B. Michel, "Untility of Transient Testing to Characterize Thermal Interface Materials," 13th THERMINIC, Sept. 17-19, Budapest, Hungary, (2007).
Images, click to enlarge
Section through chip with thermal interfaces and cooling cap.
Section through chip with thermal interfaces and cooling cap
Squeeze flow between chip and cooler with an additional channel (right). Arrows show the large flow differences due to the larger dimensions of the channel plus squeeze gap (d+h).
Squeeze flow between chip and cooler with an additional channel
Setup for mechanical and thermal measurements of thermal interface materials. Performance of HNC and flat caps are compared on this setup.
Setup for mechanical and thermal measurements of thermal interface materials
SEM of three-level hierarchical nested channel interfaces with an array size of six posts etched into silicon by a deep-trench RIE process.
SEM of three-level hierarchical nested channel interfaces
Comparison of paste pumping on flat interface (left) and HNC interface (right) showing the resistance of the HNC against paste pumping and the thinner interface that can be reached.
Comparison of paste pumping on flat interface and HNC interface
 
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