Nanowire devices

The electrical properties of different kind of architectures as well as different transistor structures based on Si nanwires are investigated in this project. The two different approaches used are the vertical and the lateral transistors.

The figure at right demonstrates the inversion in a lateral Si-nanowire FET. This was the first successful demonstration of implantation for ohmic contact formation in Si-nanowires [1].

Figure 1. Lateral nanowire FETs. Click to enlarge.

We demonstrated the first vertical surround-gate Si-nanowire transistor, see image at right. A surround-gate allows the optimal electrostatic control over the channel [2].

Figure 2. Vertical Schottky barrier FETs. Click to enlarge.

We demonstrated vertically standing, epitaxial, individual silicon nanowire field effect transistors at room temperatures, with sub-threshold slopes as low as 5 mV/decade over four orders of magnitude in current. The sub-threshold slope is a measure for the voltage needed to switch a transistor between its “on” and “off” state. In conventional transistors, the lower limit of the sub-threshold slope is 60 mV/decade at room temperature. The transistors demonstrated here make use of the internal gain of an avalanche multiplication of charge carriers. Our device represents an important advancement in pushing the limits of device performance towards extremely low-power operation. The results have been published in Applied Physics Letters [3].

Figure 3. Nanowire field effect impact ionization MOSFET with ultralow sub-threshold slope. The device can be operated as an SB-MOSFET as well as in the impact ionization mode. Click to enlarge.

 References