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The
electrical properties of different kind of architectures as well
as different transistor structures based on Si nanwires are investigated
in this project. The two different approaches used are the vertical
and the lateral transistors. |
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The
figure at right demonstrates the inversion in a lateral Si-nanowire
FET. This was the first successful demonstration of implantation
for ohmic contact formation in Si-nanowires [1].
Figure 1. Lateral nanowire FETs. Click to enlarge. |
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We
demonstrated the first vertical surround-gate Si-nanowire transistor,
see image at right. A surround-gate allows the optimal electrostatic
control over the channel [2].
Figure 2. Vertical Schottky barrier FETs. Click to
enlarge. |
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We
demonstrated vertically standing, epitaxial, individual silicon
nanowire field effect transistors at room temperatures, with sub-threshold
slopes as low as 5 mV/decade over four orders of magnitude in current.
The sub-threshold slope is a measure for the voltage needed to
switch a transistor between its “on” and “off” state.
In conventional transistors, the lower limit of the sub-threshold
slope is 60 mV/decade at room temperature. The transistors demonstrated
here make use of the internal gain of an avalanche multiplication
of charge carriers. Our device represents an important advancement
in pushing the limits of device performance towards extremely low-power
operation. The results have been published in Applied Physics Letters
[3].
Figure 3. Nanowire field effect impact ionization MOSFET with
ultralow sub-threshold slope. The device can be operated as an
SB-MOSFET as well as in the impact ionization mode. Click to
enlarge. |
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References
| [1] |
O. Hayden, M. T. Björk, H. Schmid, H. Riel, U. Drechsler,
S.F. Karg, E. Lörtscher, W. Riess, Fully-Depleted Nanowire
Field Effect Transistor in Inversion Mode, Small 3, 230 (2007). |
| [2] |
V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess,
U. Gösele, Realization of a Silicon Nanowire Vertical
Surround-Gate Field-Effect Transistor, Small 2(1) (January
2006) 85-88 (published online: 7 Nov 2005). |
| [3] |
M.T. Björk, O. Hayden, H. Schmid, H. Riel, W. Riess,
Vertical Surround-Gated Silicon Nanowire Impact Ionization
Field-Effect Transistors, Appl. Phys. Lett. 90, 142110 (2007). |
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