Nanowire device modeling

The modeling and simulation activity in our team aims at understanding the electronic transport phenomena in nanowire (NW) field-effect transistors. Another priority is the exploration of new device architectures based on nanowires.

Simulations of the electronic behavior of nanowire FETs consist of self-consistent calculations using the non-equilibrium Green's function formalism, together with a modified 1D Poisson equation that accounts for all aspects related to the lateral and vertical scaling of FET devices. In addition to these simulations, we are also developing analytically tractable models that allow easy access to device-relevant figures of merit.

Figure 1. Left panel shows metal-nanowire contact in the case of strong coupling. The metal induces gap states within the band gap of the semiconductor (see local density of state image in the lower part). As a result, the source/drain contacts resemble metallic contacts, giving rise to a device with Schottky-barrier FET behavior. Inserting an insulator, as illustrated in the left part of the figure, suppresses the metal-induced gap states. In this case, the injection of carriers occurs from an almost unaltered, semiconducting nanowire portion. Click to enlarge.

The current transport in Schottky-barrier FETs is, to a large extent, determined by the injection through the source-side Schottky diode. The presence of this barrier leads to larger inverse subthreshold slopes and lower on-currents than those of conventional FETs. It was shown that the carrier injection can be significantly increased using ultrathin NW diameters and gate oxide thicknesses [1]. However, the improved carrier injection leads to a large off-state leakage due to the ambipolar operation of SB-FETs. Particularly for high-mobility, small band-gap materials, this is problematic and potentially makes these materials unusable.

We are working on contact schemes in a side-contact configuration, where it is possible to insert a barrier layer between the electrode and the nanowire [2], which significantly suppresses the ambipolar operation. As a result, such contacts, if designed properly, potentially allow the use of metallic electrodes in nanowire FETs without the drawback of a large off-state leakage due to ambipolar operation.

Figure 2. Power delay product of a nanowire FET exhibiting one-dimensional transport as a function of channel length and gate oxide thickness. By scaling down the gate oxides, the quantum capacitance limit is reached, where the total gate capacitance is dominated by the semiconductor or quantum capacitance as opposed to the geometrical oxide capacitance. In this limit a substantial scaling benefit is obtained. Click to enlarge.

Nanowire FETs with doped source/drain contacts potentially facilitate ultimately scaled transistors if nanowires with ultrathin diameters are used in a wrap-gate architecture. In such NW FETs it is likely that the transport becomes one-dimensional (1D). Besides all issues related to fabrication, variability, etc., an important question is how the 1D transport manifests itself in the device performance. It is known that, in 1D FETs with very thin gate insulators, the so-called quantum capacitance limit can be reached where the charge in the channel no longer increases with increasing oxide capacitance. At first glance one might think that this is detrimental to device performance. However in this limit the power delay product, i.e. the energy needed for switching, is substantially reduced [3]. This significant performance benefit is only accessible in 1D structures, making nanowires a premier choice for ultimately scaled transistor devices.

Figure 3. Conduction and valence band profile in a band-to-band tunneling nanowire FET. The device consists of an n-doped source, an intrinsic channel and a p-doped drain contact. The main panel of the figure shows the spectral distribtuion of holes along the device. Holes are injected from the conduction band of the source contact into the channel via band-to-band tunneling only in a small energetic window. The high and low energetic tails of the source Fermi distribution are cut off. It is this band-pass filter behavior that allows inverse subthreshold slopes steeper than 60 mV/dec to be obtained, as illustrated in the inset. Click to enlarge.

The limitation to a minimum inverse subthreshold slope of S=60 mV/dec of any conventional FET is a major obstacle to further reducing the supply voltage and hence the power consumption of integrated circuits. Lowering the supply voltage leads either to devices with a deteriorated on-state or to significantly increased off-state leakage. Therefore, devices exhibiting a slope of S<60 mV/dec and a high on-state performance are highly desirable. At present, the most promising device concepts are the tunneling transistor and the impact ionization FET. Regarding tunneling FETs we are studying the transport and optimization of device performance. As it turns out, 1D structures such as nanowires are particularly well suited for tunneling FETs [2,4]. Work regarding the scaling behavior of impact ionization FETs is in progress.