Metal-oxide semiconductor field-effect transistors (MOSFETs) built during the past 50 years used silicon, an insulating layer of silicon dioxide, and a metallic gate electrode made of polysilicon. Reducing the lateral dimensions of the transistor allows the economical benefits to be combined with improved performance. This method has driven the CMOS technology throughout its golden era. Reducing the geometrical scaling of the transistors implies, however, a reduction of critical dimensions such as dielectric thickness, an approach that can no longer be taken. Owing to different leakage mechanisms, the dissipated power at the device level has become the performance-limiting factor.
Our research focuses first on CMOS performance enhancements via materials innovation instead of pure scaling. Used as a channel, compound semiconductors (GaAs, Ge, InGaAs, etc) offer enhanced carrier transport compared to silicon.
Future chips will also combine more and more functions for RF connectivity, built-in sensors, data storage, etc. Adding functionalities to CMOS circuits and chips will also require intense materials development. For many years we have been developing processes to deposit crystalline oxides directly on silicon as a starting point to integrate functional oxides on silicon.
To support this effort, we have developed the appropriate molecular beam epitaxy (MBE) infrastructure, which combines clean UHV conditions with a high degree of versatility in growing new materials. We operate a world-unique MBE cluster tool, which integrates III-V, SiGe, oxides deposition and surface analysis capabilities. Wafers from 2 to 8” in size can be processed, allowing us to send wafers through state-of-the-art processing lines.